Stock material or miscellaneous articles – Composite – Of quartz or glass
Reexamination Certificate
2000-10-16
2003-04-01
Lam, Cathy (Department: 1775)
Stock material or miscellaneous articles
Composite
Of quartz or glass
C428S432000, C428S446000, C257S629000
Reexamination Certificate
active
06541117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon epitaxial wafer used for fabrication of a semiconductor device such as IC, LSI or the like, and a method for producing it.
2. Description of the Related Art
Along with a recent tendency to increase the degree of integration, there has been an increasing demand for silicon wafers having high quality. As a wafer for fabrication of a device, a silicon epitaxial wafer having a very excellent quality has been mainly used.
FIG. 1
shows a section of a silicon epitaxial wafer, which is one example of an epitaxial silicon wafer
3
wherein a epitaxial layer
2
is grown on a silicon wafer
1
as a substrate. It is important to obtain a silicon epitaxial wafer having more excellent quality in order to achieve finer pattern, higher density, higher speed and higher yield in a semiconductor integrated circuit.
For example, a silicon epitaxial wafer is used for fabrication of Metal Oxide Semiconductor (MOS) type semiconductor apparatus, so-called MOS device or the like. FIGS.
3
(
a
), (
b
) are views showing a structure of one example of MOS device, which is one example of MOS device wherein a lot of LOCOS patterns are aligned. FIG.
3
(
a
) is a top plan view of the MOS device, and FIG.
3
(
b
) is a sectional view of the MOS device. In the figure, a gate oxide film
4
is formed on the silicon epitaxial wafer
3
as a base, on which a gate electrode
5
made of a polycrystalline silicon is formed. Both ends of the gate oxide film
4
is an oxide film
6
called so-called LOCOS oxide film that is a thick insulation separation film insulating each of devices electrically.
One of methods for evaluating quality of a silicon epitaxial wafer used for fabrication of such MOS device is dielectric breakdown property for confirming electrical characteristics of oxide film in MOS device. Examples of other methods include methods for evaluating quality such as Liquid Crystal Thermal Mapping (G. J. West, “A simple technique for analysis of ESD failure of dynamic RAMs using liquid crystals”, in Proc. IEEE Int. Rel. Phys. Symp., 185(1982).), Visible and Infrared radiation emission (K. S. Wills, C. Duvvury, and O. Adams, “Photoemission testing for ESD failures, advantages and limitations”, in EOS/ESD Symp. Proc., 53(1988).) IR microscopy (C. E. Stephens and C. T. Amos, “A study of EOS in microcircuits using the infra-red microscope”, in EOS/ESD Symp. Proc., 219(1986).), or the like. They are very effective means for specifying a certain failure part in MOS device.
However, there have been sometimes occurred a failure called so-called Erratic phenomenon wherein a failure part in a device changes with time in a MOS device. The wafer where Erratic phenomenon occurs may lead to a problem that a yield is reduced in fabrication of MOS device. According to the above-mentioned method for analyzing failures, a failure part can be specified, but it is quite difficult to analyze Erratic phenomenon. Because, even though information of a failure part can be obtained each time, the failure part changes with passing time. There have been found no wafers wherein Erratic phenomenon can be prevented, and no condition for production of the wafer.
As methods for measuring reliability of the oxide film conventionally used, TZDB (Time Zero Dielectric Breakdown) method, and TDDB (Time Dependent Dielectric Breakdown) method are known. In these methods, electric field is applied to a semiconductor substrate having MOS structure in direction of accumulation so that carrier can be collected right under the gate oxide film for evaluation.
However, in an actual device, a diffusion layer is formed to the depth of several &mgr;m from the surface of the silicon wafer right below the gate oxide film, and is used as a device area. These methods for evaluating electrical failure only with information from a gate oxide film, do not always reflect yield of actual device.
As methods for evaluation compensating the disadvantage, there have been developed methods for evaluation using OBIC or EBIC described below (See Japanese patent application laid-open(kokai) No. 11-216683). The method comprising applying voltage to a semiconductor substrate having MOS structure in a direction of formation of depletion layer, and measuring OBIC or EBIC generated in MOS device by irradiating with laser or electron beam with varying applied voltage.
According to the method, evaluation of not only a gate oxide film but also a substrate surface layer part right below the gate oxide film are possible, and thus characteristic failure that cannot be detected by conventional TZDB method or TDDB method.
The inventors tried evaluation of silicon epitaxial wafer by the method, and found that there is an apparent difference in results of evaluation among wafers wherein good evaluation results can be obtained according to conventional method, namely evaluation of quality with higher sensitivity compared with a conventional method is possible.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above-mentioned problems, and an object of the present invention is to provide a silicon epitaxial wafer wherein Erratic phenomenon that failure part changes with passing time in a MOS device does not occur, and a method for producing it.
Another object of the present invention is to provide a silicon epitaxial wafer wherein good characteristics of certain level or more can be achieved when evaluating MOS characteristics by a method for evaluation with high sensitivity by the above-mentioned OBIC or EBIC.
In order to achieve the above objects, the present invention provides a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein Erratic phenomenon does not occur in a MOS device fabricated on the silicon epitaxial wafer.
As described above, according to the present invention, the silicon epitaxial wafer wherein Erratic phenomenon does not occur in a MOS device fabricated on the silicon epitaxial wafer can be provided, so that yield of the MOS device can be significantly improved.
The present invention also relates to a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer is 1×10
17
to 1×10
18
atoms/cm
3
.
As described above, a silicon epitaxial wafer wherein oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer is 1×10
17
to 1×10
18
atoms/cm
3
can be a silicon epitaxial wafer wherein Erratic phenomenon can be surely prevented.
The present invention also relates to a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer characterized in that OBIC image or EBIC image of MOS capacitor produced on the silicon epitaxial wafer begins to be observed when the voltage applied to the MOS capacitor is 20 MV/cm or more.
As described above, in the silicon epitaxial wafer characterized in that OBIC image or EBIC image of MOS capacitor produced on the silicon epitaxial wafer begins to be observed when the voltage applied to the MOS capacitor is 20 MV/cm or more, namely, oxide dielectric breakdown voltage is 20 MV/cm or more, a margin until a failure such as Erratic phenomenon occurs is larger compared to an operating condition of an actual MOS device. Accordingly, an excellent performance wherein substantially no Erratic phenomenon occurs can be achieved.
The present invention also relates to a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer is 5×10
16
to 5×10
17
atoms/cm
3
.
As described above, a silicon epitaxial wafer wherein oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer is 5×10
16
to 5×10
17
atoms/cm
3
has good
Lam Cathy
Oliff & Berridg,e PLC
Shin-Etsu Handotai & Co., Ltd.
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