Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection
Reexamination Certificate
2001-11-05
2004-09-14
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Device protection
C257S355000, C257S358000, C257S359000, C257S360000, C257S363000, C257S373000, C257S374000
Reexamination Certificate
active
06791122
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to the field of electrostatic discharge (ESD) protection circuitry, and more specifically, improvements for silicon controlled rectifier (SCR) structures in the protection circuitry of an integrated circuit (IC).
BACKGROUND OF THE INVENTION
Integrated circuits (IC's) and other semiconductor devices are extremely sensitive to the high voltages that may be generated by contact with an ESD event. As such, electrostatic discharge (ESD) protection circuitry is essential for integrated circuits. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (several amperes) of a short duration (typically, 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC's and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.
The ESD problem has been especially pronounced in complementary metal oxide semiconductor (CMOS) field effect transistors. To protect against these over-voltage conditions, silicon controlled rectifiers (SCR) and other protection devices such as the grounded-gate NMOS have been incorporated within the circuitry of the CMOS IC to provide a discharge path for the high current produced by the discharge of the high electrostatic potential. Prior to an ESD event, the SCR is in a nonconductive state. Once the high voltage of an ESD event is encountered, the SCR then changes to a conductive state to shunt the current to ground. The SCR maintains this conductive state until the voltage is discharged to a safe level.
FIG. 1A
depicts a schematic diagram of a prior art SCR included within an integrated circuit to provide ESD protection as illustratively provided in U.S. Pat. No. 5,465,189 and U.S. Pat. No. 5,502,317. In particular, an illustrative prior art integrated circuit
100
has an SCR protection circuit
101
connected from a pad
148
to ground. The pad
148
is also connected to the protected circuitry of the IC, optionally through a current limiting resistor R
L
. The SCR protection circuit
101
comprises a trigger device
105
and an SCR
102
. The SCR
102
further comprises a NPN transistor T
1
131
and a PNP transistor T
2
132
. In particular, the SCR protection device
101
includes an anode
122
, which is connected to the pad
148
, and to one side of a resistor R
B2
142
. The resistor R
B2
142
represents the resistance of the N-well, which is seen at the base of a PNP transistor of the SCR
102
, as is discussed in further detail below. Additionally, the anode
122
is coupled to an emitter
108
of a PNP transistor T
2
132
, which is parallel to the N-well resistance R
B2
142
. A first node
134
includes the base of the PNP transistor T
2
132
, the other side of the resistor R
B2
142
, and the collector of the NPN transistor T
1
131
. Additionally, the collector
106
of the PNP transistor T
2
132
is connected to a second node
136
, which is also connected to the base
106
of the NPN transistor T
1
131
, and to one side of a resistor R
B1
141
. The other side of resistor R
B1
141
is connected to a third node
124
that is grounded, and which serves as the cathode. Furthermore, the emitter
112
of the NPN transistor T
1
131
is also connected to the grounded third node
124
.
The triggering device
105
is illustratively a grounded gate NMOS (GGNMOS) transistor, which has its source
127
and gate
126
coupled to ground. Additionally, the drain
129
and source
127
of the GGNMOS transistor
105
are respectively coupled to the collector
110
and the emitter
112
of the NPN transistor T
1
131
. Furthermore, the gate
126
and source
127
of the GGNMOS transistor are also connected to the grounded third node
124
(i.e., cathode of the SCR).
FIG. 1B
depicts a cross-sectional view of a prior art low voltage triggering SCR (LVTSCR) device as depicted in FIG.
1
A. Furthermore,
FIG. 1B
illustratively includes the schematic diagram of the SCR circuit as related to the P and N doped regions of the IC
100
. Specifically, the integrated circuit
100
includes a P-type substrate
103
into which an N-well
104
and P-well
106
are formed adjacent to each other. A junction
107
is formed at the adjoining boundary of the N-well
104
and the P-well
106
.
Within the N-well
104
, a first P+ region
108
is formed. Furthermore, within the P-well
106
, a first N+ region
112
and a second P+ region
114
are formed thereupon. In addition, a second N+ region
110
is formed over both the P-well
106
and N-well
104
regions such that the second N+ region
110
overlaps the junction
107
of the P-well and N-well regions
106
and
104
. The regions denoted P+ an N+ are regions having higher doping levels than the N-well and P-well regions
104
and
106
.
Shallow trench isolation (STI) is used in most state-of-the-art CMOS processing technologies to laterally separate the high-doped regions. Shallow trench isolation is performed prior to forming the high P+ and N+ doped regions. In particular, trenches are etched in specific areas from the silicon surface, and an insulator material (e.g., silicon dioxide (SiO
2
)) is deposited to fill the trenches. A gate dielectric layer such as silicon dioxide (SiO
2
)
130
is grown over the parts of the surface exposing bare silicon. A gate electrode material (e.g. poly silicon) is deposited over the entire surface. The gate electrode material and the gate dielectric are structured by a photo-lithographical masking followed by an etching step. After the masking and etching steps, only the photo patterned area of the gate dielectric
130
and the gate electrode
128
remain, as illustrated. Then, the silicon between the STI receives ion implants to form the high-doped P and N regions as discussed above.
Specifically, after performing the STI and creating the high-doped regions, a first STI region
116
1
is positioned illustratively to the left of the first P+ doped region
108
. Additionally, a second STI region
116
2
is positioned between the first P+ region
108
and the second N+ region
110
. Furthermore, a third STI region
116
3
is positioned between the first N+ region
112
and the second P+ region
114
, and a fourth STI region
116
4
is positioned to the left of the second P+ region
114
.
The gate
126
of the GGNMOS transistor
105
separates the first and second N+ regions
112
and
110
. Furthermore, the GGNMOS transistor
105
is used to “trigger”, i.e., turn on the SCR. In particular, the GGNMOS transistor
105
is an N-channel MOS transistor, which includes a drain
129
and source
127
, which are respectively formed by the second N+ region
110
and the first N+ region
112
. The NMOS-channel is formed at the surface of the P-well region
120
between the first and second N+ regions
112
and
110
. Additionally, since the gate
126
is grounded, the P-well region
120
is prevented from forming the NMOS-channel between the first and second N+ regions
112
and
110
, thereby preserving the functionality of the SCR's bipolar transistor T
1
131
.
The NPN transistor T
1
131
has its emitter formed by the first N+ region
112
, the base formed by the P-well
106
, and the collector formed by the N-well
104
, which is electrically in parallel with the second N+ region
110
(NMOS drain). The PNP transistor T
2
132
has its emitter formed by the first P+ region
108
, the base formed by the N-well
104
and the second N+ region
110
, and the collector formed by the P-well
106
. It should be noted that the N-well
104
and the drain region
11
Armer John
Avery Leslie R.
Mergens Markus P. J.
Russ Christian C.
Verhaege Koen G. M.
Burke, Esq. William J.
Sarnoff Corporation
Tran Minhloan
Tran Tan
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