Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2006-05-16
2006-05-16
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S077000, C257S289000
Reexamination Certificate
active
07045879
ABSTRACT:
The principal surface of a p-type SiC substrate (1) is formed of a face intersecting (0001) Si-face at 10 to 16°. An n+source region (2) and an n+drain region (3) are formed in a surface layer portion at the principal surface of the p-type SiC substrate (1) so as to be separated from each other. A gate electrode (5) is formed on a gate oxide film (4) on the principal surface of the p-type SiC substrate (1).
REFERENCES:
patent: 6097039 (2000-08-01), Peters et al.
patent: 6384428 (2002-05-01), Oono et al.
patent: 2001/0038108 (2001-11-01), Kitabatake et al.
patent: A-2000-294777 (2000-10-01), None
Amano Shinji
Endo Takeshi
Hisada Yoshiyuki
Ichimiya Ayahiko
Mitsuoka Yoshihito
Denso Corporation
Jackson Jerome
Posz Law Group , PLC
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