Silicon carbide semiconductor device and method of...

Details Silicon carbide semiconductor device and method of... Silicon carbide semiconductor device and method of...

2002-03-28

2003-04-22

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Making regenerative-type switching device

Having field effect structure

C438S138000, C438S173000, C438S193000, C438S194000, C438S195000, C438S931000, C257S077000, C257S134000, C257S135000, C257S260000, C257S263000

Reexamination Certificate

active

06551865

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a silicon carbide semiconductor device such as a junction field-effect transistor (JFET). In addition, this invention relates to a method of fabricating a silicon carbide semiconductor device such as a JFET.
2. Description of the Related Art
U.S. Pat. No. 6,117,735 corresponding to Japanese patent application publication number 11-195655 discloses a method of forming a silicon carbide vertical FET in which ion implantation is implemented while a first mask and a second mask overlapping the first mask are used. As a result of the ion implantation, a first conductivity type impurity region is defined by one end of a certain portion of the first mask. The portion of the first mask and the second mask are then removed so that a second conductivity type impurity region is defined by another portion of the first mask. Thus, the first conductivity type impurity region and the second conductivity type impurity region are formed on a self-alignment basis. In the case where a mask including a tapered end portion is used and ion implantation is conducted with different accelerating-field voltages, the first conductivity type region and the second conductivity type region can be formed on a self-alignment basis using only one mask. The threshold voltage can be adjusted by controlling the impurity concentration of the channel region. The silicon carbide vertical FET is of a normally-off type.
U.S. Pat. No. 6,057,558 corresponding to Japanese patent application publication number 10-308512 discloses a trench gate type power MOSFET including a thin film of silicon carbide which defines a side of a trench. Specifically, the power MOSFET includes an n-type thin semiconductor film defining a side of the trench, and a gate oxide film occupying a bottom of the trench. The power MOSFET further includes an n
−
-type epitaxial layer and a p-type epitaxial layer between which an n
+
-type epitaxial layer extends. The p-type epitaxial layer, the n
+
-type epitaxial layer, and the n
−
-type epitaxial layer compose a pn
+
n
−
diode. The impurity concentration and the thickness of the n
+
-type epitaxial layer are chosen so that the withstand voltage of the pn
+
n
−
diode will be lower than the withstand voltage of a surface of the gate oxide film in the trench bottom. As a result, the pn
+
n
−
diode undergoes avalanche breakdown before the trench bottom does. Therefore, it is possible to prevent destruction of the gate oxide film.
Heinz Mitlehner et al have reported “Dynamic characteristics of high voltage 4H-SiC vertical JFETs”, 1999 IEEE, pages 339-342. Specifically, Heinz Mitlehner et al fabricated fully implanted SiC VJFETs on n-type epilayers grown on the Si(0001)-face of n-type 4H-SiC substrates. The epilayers were grown in two steps. The first epilayer was formed. After registration masks were defined, the first epilayer was exposed to ion implantation so that the buried p-layer was implanted with aluminum. Then, the second epilayer creating the channel and pinch off region was grown onto the first epilayer. The p-gate region was implanted over the whole cell area. In three etching steps, the gate overlay, the source area and the short connection of the source region to the buried p-layer were defined. To avoid breakdown due to field crowding at the edges, a JTE-edge termination was used. After the wafers were annealed, a field oxide was deposited. Ni-contacts on back and front were defined via lithography and lift-off. After a short contact anneal, the insulation oxide was deposited and patterned via dry etching. Finally, the metallization was thermally evaporated and patterned by wet etching.
Japanese patent application publication No. 11-274173 discloses a method of fabricating a silicon carbide semiconductor device in which a mask member is formed on an n
−
-type silicon carbide epitaxial layer. Prescribed areas of the mask member are provided with openings which have inclined side surfaces. Ion implantations into the n
−
-type silicon carbide epitaxial layer via the openings are performed so that p
−
-type silicon carbide base regions and n
+
-type source regions are formed therein. The n
+
-type source regions are smaller in junction depth than the p
−
-type silicon carbide base regions. Since only one mask is used in this way, the formation of the p
−
-type silicon carbide base regions and the n
+
-type source regions is based on self-alignment. Therefore, the positions of the p
−
-type silicon carbide base regions and the n
+
-type source regions are accurate.
Japanese patent application publication number 8-288500 discloses a silicon carbide semiconductor device including a planar-type pn junction. An edge of the planar-type pn junction is of a thin flat shape to suppress concentration of electric field. The pn junction is formed by ion implantation using a mask which is made as follows. After a process of providing close adhesion between a photoresist film and a mask film is implemented, the combination of the films is exposed to isotropic etching to form the mask.
SUMMARY OF THE INVENTION
It is a first object of this invention to provide a silicon carbide semiconductor device which is excellent in on-resistance (on-state resistance), withstand voltage, and avalanche breakdown.
It is a second object of this invention to provide a method of fabricating a silicon carbide semiconductor device which is excellent in on-resistance, withstand voltage, and avalanche breakdown.
A first aspect of this invention provides a method of fabricating a silicon carbide semiconductor device. The method comprises the steps of forming a semiconductor layer (
2
) on a main surface of a semiconductor substrate (
1
), the semiconductor layer (
2
) and the semiconductor substrate (
1
) being of a first conductivity type, the semiconductor layer (
2
) being made of silicon carbide, the semiconductor substrate (
1
) being made of silicon carbide, the semiconductor layer (
2
) being higher in resistivity than the semiconductor substrate (
1
); forming a first gate region (
3
) in a surface portion of the semiconductor layer (
2
), the first gate region (
3
) being of a second conductivity type different from the first conductivity type; forming a channel layer (
5
) of the first conductivity type on the semiconductor layer (
2
) and the first gate region (
3
); forming a source region (
6
) of the first conductivity type in the channel layer (
5
), the source region (
6
) being opposed to the first gate region (
3
); forming a second gate region (
7
) in a surface portion of the channel layer (
5
), the second gate region (
7
) being of the second conductivity type and containing a positional range opposed to the source region (
6
); forming a recess (
8
) in the channel layer (
5
), the recess (
8
) extending through the second gate region (
7
) and the source region (
6
) and reaching the first gate region (
3
); forming a first gate electrode (
9
,
33
,
42
), a source electrode (
9
,
32
,
41
), and a second gate electrode (
10
,
32
,
43
), the first gate electrode (
9
,
33
,
42
) being electrically connected with the first gate region (
3
), the source electrode (
9
,
32
,
41
) being electrically connected with the source region (
6
), the second gate electrode (
10
,
32
,
43
) being electrically connected with the second gate region (
7
); and forming a drain electrode (
12
) on a back surface of the semiconductor substrate (
1
). The step of forming the source region (
6
) and the step of forming the second gate region (
7
) comprise the sub-steps of (a) placing first and second mask films (
21
,
22
) on the channel layer (
5
), the first mask film (
21
) being covered with the second mask film (
22
); (b) forming first and second openings (
21
A,
22
A) in the first and second mask films (
21
,
22
) respectively; (c) implanting first ions into a first predetermined place in the channel layer (
5
) w

Affiliated with

Also associated with

Rating

Silicon carbide semiconductor device and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon carbide semiconductor device and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon carbide semiconductor device and method of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3026498