Silicon carbide semiconductor device

Details Silicon carbide semiconductor device Silicon carbide semiconductor device

1998-11-27

2001-07-17

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S331000, C257S339000, C257S341000, C257S356000

Reexamination Certificate

active

06262439

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a silicon carbide semiconductor device and in particular relates to a vertical type insulated gate field effect transistor for large electric power use (hereinafter, referred to as “vertical type power MOSFET).
2. Related Art and Discussion
FIG. 16
shows a sectional constitution of a vertical type power MOSFET described in JP-A-7-326755. The conventional vertical type power MOSFET is explained with reference to FIG.
16
.
In
FIG. 16
, an SiC substrate
104
is formed by successively depositing an n
−
-type epitaxial layer
102
and a p-type epitaxial layer
103
on an n
+
-type monocrystalline SiC semiconductor substrate
101
.
An n
+
source region
105
constituting a semiconductor region is formed in the p-type epitaxial layer
103
by ion implantation or the like. Also, a trench
106
passing through the n
+
source region
105
and the p-type epitaxial layer
103
and reaching the n
−
-type epitaxial layer
102
is formed by etching. Inside the trench
106
, a gate thermal oxide film (insulation film)
107
is formed, and a gate electrode layer
108
is formed thereon. Also, a source electrode layer
110
constituting a first electrode layer is formed on an interlayer insulation film
109
, the surface of the n
+
-type source region
105
and the surface of the p-type epitaxial layer
103
. A drain electrode layer
111
constituting a second electrode layer is formed on the back surface of the semiconductor substrate
104
.
In the construction described above, the surface of the p-type epitaxial layer
103
on the side surface of the trench
106
is a channel region. When a positive voltage is impressed on the gate electrode
108
and a channel is formed in the side surface of the p-type epitaxial layer
103
, current flows between the source and the drain.
However, when a high voltage is impressed between the source and the drain while the vertical type power MOSFET is in an off state (i.e., no voltage is applied to the gate electrode), the working life of the gate oxide film
107
is shortened because it may suffer some damage or a blocking voltage thereof becomes small comparing to a design value.
To solve the above-mentioned problems, the inventors built a prototype of the conventional vertical type power MOSFET and studied it.
When a voltage is applied between the source and the drain during the off state of the vertical type power MOSFET, a depletion layer is produced at a PN junction portion between n
−
-type epitaxial layer
102
and the p-type epitaxial layer
103
, whereby an electric field is generated. The distribution of the electric field depends on impurity concentrations of the n
−
-type epitaxial layer
102
and the p-type epitaxial layer
103
and the magnitude of voltage applied between the source and the drain. The blocking voltage of the power MOSFET is determined by the condition at which a punch-through phenomenon occurs, that is, the depletion layer extending on a side of the p-type epitaxial layer
103
reaches the n
+
-type source region
105
.
It was confirmed that a measured blocking voltage lowers rather than a design blocking voltage in the prototype of the conventional power MOSFET. As the cause thereof, it is considered that the side surface of the trench
106
is formed not to be perpendicular to the surface of the SiC substrate
104
but to be inclined to some extent with respect thereto.
FIG. 17
shows a schematic view of the vertical type power MOSFET in which a high voltage is impressed between the source and the drain during the off state thereof. The reason why the measured blocking voltage lowers is described with reference to FIG.
17
.
The depletion layer is produced at the PN junction portion between the n
−
-type epitaxial layer
102
and the p-type epitaxial layer
103
. The end portion of the depletion layer which makes contact to the surface of the trench
106
(hereinafter, referred to as “depletion layer end portion) is terminated in a state that it is substantially perpendicular to the surface of the trench
106
. For this reason, if the side surface of the trench
106
is perpendicular to the surface of the SiC substrate
104
, the depletion layer end portion will be terminated in a state that it is substantially parallel to the surface of the SiC substrate
104
. However, when the trench
106
is formed by etching, in practice, the side surface of the trench
106
is formed to be inclined to some extent with respect to the surface of the SiC substrate
104
. Therefore, as shown in
FIG. 17
, the depletion layer end portion is terminated in a state that it is curved in the vicinity of the trench
106
.
As a result, the depletion layer end portion reaches the boundary between the p-type epitaxial layer
103
and the n
+
-type source region
105
earlier than the other portion of the depletion layer. For this reason, it is considered that a punch-through phenomenon occurs at an SiO
2
/SiC interface which is an interface with the gate thermal oxide film
107
comprising an SiO
2
film earlier than the other portion, whereby the actual blocking voltage lowers rather than the design value.
To confirm this consideration, a source-drain voltage causing the punch-through phenomenon was measured while a gate voltage is changed. As a result, it was confirmed that the source-drain voltage causing the punch-through phenomenon has strong dependence upon the gate voltage. This result means that the punch-through phenomenon mainly occurs at the SiO
2
/SiC interface and is in agreement with the above-mentioned consideration.
In view of the above, the inventors concluded that the cause of the gate oxide film damage and the shortened working life of the gate oxide film is in that current generated by the punch-through phenomenon is greatly accelerated along the SiO
2
/SiC interface and functions as a hot carrier, thereby deteriorating the SiO
2
/SiC interface and the gate oxide film.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a silicon carbide semiconductor device which can prevent the working life of the gate oxide film from being shortened.
To achieve this object, in the silicon carbide semiconductor device according to the present invention, a semiconductor substrate made of single crystal silicon carbide is formed by successively depositing a first conductivity type second semiconductor layer and a second conductivity type third semiconductor layer on a first conductivity type first semiconductor layer. A first conductivity type semiconductor region is formed in a surface portion of the third semiconductor layer and is divided into first and second regions. A trench is formed in the semiconductor substrate so as to penetrate the third semiconductor layer and reach the second semiconductor layer. The first region is disposed around the trench so that the side surface of the first region is exposed to the trench. The second region is disposed to be distant from the trench and to be adjacent to the first region. The thickness of the third semiconductor layer between the second region and the second semiconductor layer is made thinner than that of the third semiconductor layer between the first region and the second semiconductor layer.
When the thickness of the third semiconductor layer is set as described above, the punch-through phenomenon occurs on a second region side. As a result, it is possible to prevent the punch-through phenomenon from occurring at an interface between a gate insulation film formed in the trench and the third semiconductor layer, i.e., at an SiO
2
/SiC interface. Therefore, it is possible to prevent the working life of the gate insulation film from being shortened.
Alternatively, the second region can be formed by metal silicide or metal carbide.
Further, a stepped portion may be formed on the surface of the third semiconductor layer so that the surface of the third semiconductor layer in the region for the first region to be formed is

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