Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-12-21
2003-04-29
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S695000, C438S697000, C438S700000, C438S706000, C438S723000, C438S724000
Reexamination Certificate
active
06555476
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and particularly to chemical mechanical polish (CMP) stops used for isolation dielectric planarization.
BACKGROUND: CMP
Chemical mechanical polishing (CMP) is a planarization technique which has become increasingly important in integrated circuit processing in the 1990s. CMP, unlike most other planarization techniques, provides global planarization. This global planarization avoids problems of step coverage, and hence helps achieve the numerous multiple layers of metallization which are now desired. Global planarization also improves lithographic resolution, by removing constraints on the depth of field.
In a CMP process, a wafer is polished in a slurry of a very fine abrasive (typically alumina, A1203). The slurry has a chemical composition which accelerates removal of the top surface. For example, for removal of tungsten an acidic and oxidizing slurry is used; this helps to convert the surface of the tungsten into a tungsten oxide, which is easily removed by the mechanical polishing operation. For removal of dielectrics, a basic chemistry is more typically used.
General discussion of CMP techniques can be found in Ali et al., “Chemical-mechanical polishing of interlayer dielectric: a review,” which appeared at page 63 of the October 1994 issue of SOLID STATE TECHNOLOGY, and references cited therein. (Note, however, that this article is particularly focussed on dielectric removal.) Additional discussion can be found in DeJule, “Advances in CMP,” SEMICONDUCTOR INTERNATIONAL, November 1996, at pages 88 and following, and references cited therein; and in Kim et al., “Optimized Process Developed for Tungsten CMP,” SEMICONDUCTOR INTERNATIONAL, November 1996, at pages 119 and following. All of these materials are hereby incorporated by reference.
BACKGROUND:SILICON NITRIDE AS CMP STOP
To provide the degree of uniformity which is desirable in planarizing integrated circuit processes, CMP stop layers are commonly used with CMP processes. One such CMP stop which is frequently desired is for oxide polishing. This is commonly done by including islands of silicon nitride, and using a slurry which achieves some selectivity to the nitride. However, the selectivities which are achieved with standard slurries are small, only of the order of 4 to 1 or so.
Current state of the art uses silicon nitride as both a silicon etch hardmask, and as a CMP stop layer for chemical-mechanical polishing (CMP). Since the removal selectivity of silicon dioxide to silicon nitride is only 4:1 or 5:1 using industry-accepted slurries, the silicon nitride layer is not an effective CMP polish stop layer. Non-uniformity due to polish and pattern effects can cause the dielectric SiO2 and silicon nitride over small isolated active device features to be polished much more quickly than other features, thus causing damage to these small active regions.
Some attempts have been made to achieve higher oxide: nitride selectivities by using other chemistries. One example of this is a chemistry in which the standard SS25 silica polishing slurry is modified by the addition of tetramethyl ammonium fluoride. However, the use of silicon nitride requires either a patterned etchback approach (which requires additional lithography steps) or the use of CMP slurries which include chemicals to passivate the silicon nitride surface and provide high selectivity in CMP removal of SiO2, The patterned etchback approach is more expensive than other approaches. High selective slurries are not in mass production and have not yet gained wide industry acceptance, partly because they are difficult to clean from the wafer surface after CMP processing, and they have limited shelf and pot lives.
CMP Process With Silicon Carbide Polish Stop Layers
The present application discloses innovations which use silicon carbide layers in CMP process, or alternatively, a silicon carbonitride or silicon carboxide. It has been found that standard polishing chemistries will very easily give an extremely high selectivity (50 to 1 or better) between silicon dioxide and silicon carbide. This means that non-uniformities in oxide thickness or in polish rate will be smoothed out when the faster etching areas can be covered by polish stop layers. It has also been found that silicon nitride can also be polished selectively with respect to silicon carbide, with a polish rate ratio which is greater than 12 to 1. One particularly important embodiment of the disclosed process is to provide a polish stop layer for planarization of the isolation dielectric, such as shallow trench isolation, prior to formation of transistors. A layer of silicon carbide is deposited and patterned to serve as a hardmask for the trench etch. After filling of the trenches with dielectric, the silicon carbide serves as a polish stop, allowing a smoother planarization than is otherwise possible. Using a dummy moat is required with this solution.
Advantages of the disclosed methods and structures include:
additional (addition to moat pattern) patterned etch steps are not needed;
slurries with wide industry acceptance can be used;
less expensive than currently accepted approaches that use silicon nitride and reverse moat pattern and etchback;
requires fewer process steps than patterned etchback approaches;
compatible with existing CMP slurries;
compatible with pads which have wide industry acceptance.
REFERENCES:
patent: 4929837 (1990-05-01), DiVita et al.
patent: 4954142 (1990-09-01), Carr et al.
patent: 5084071 (1992-01-01), Nenadic et al.
patent: 5317346 (1994-05-01), Garcia
patent: 5356513 (1994-10-01), Burke et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5510652 (1996-04-01), Burke et al.
patent: 5693234 (1997-12-01), Peters
patent: 5933748 (1999-08-01), Chou et al.
patent: 5958795 (1999-09-01), Chen et al.
patent: 5960297 (1999-09-01), Saki
patent: 5966616 (1999-10-01), Woerlee
patent: 4310345 (1994-10-01), None
patent: 545263 (1993-06-01), None
patent: 404213857 (1992-08-01), None
Boos et al., Dry etching silicon carbide in plasma reactor—using chlorine-contg. gas for reactive ion etching and silica di:oxide mask, English Abstract of DE 4310345 A1, Oct. 6, 1994, 2 pages.*
IBM Technical Disclosure Bulletin, III-V Semiconductor Ion Implantation Annealing Capping, Dec. 1, 1986, vol. 29, No. 7, 3 pages.*
Chemical-Mechanical Polishing of Interlayer Dielectric: A Review; Ali et al.; Solid State Technology, Oct. 1994; pp. 63-70.
Optimized Process Developed for Tungsten CMP; Kim et al.; Semiconductor International; Nov. 1995; pp. 119-123.
Advances in CMP; DeJule; Semiconductor International; Nov. 1996; pp. 88-98.
Edwards Henry L.
Olsen Leif C.
Swanson Leland S.
Brady W. James
Hoel Carlton H.
Powell William A.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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