Silicon buffered shallow trench isolation

Details Silicon buffered shallow trench isolation Silicon buffered shallow trench isolation

2007-07-03

2007-07-03

Smoot, Stephen W. (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257SE21547

Reexamination Certificate

active

10755746

ABSTRACT:
A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is formed in a selective epitaxial growth (SEG) process. The SEG process can be a CVD or MBE process. Capping layers can be used above the strained silicon layer.

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