Semiconductor device manufacturing: process – Gettering of substrate
Reexamination Certificate
1999-09-27
2003-05-27
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Gettering of substrate
Reexamination Certificate
active
06569749
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of creating gettering sites for metallic impurities within the subsurface of a wafer substrate in-situ through epitaxial deposition. Such wafers are suitable for device fabrication in low temperature integrated circuit (IC) processes of future generation high density devices.
2. Discussion of Related Art
In the manufacture of electronic components from semiconductive wafers, it is known that impurities introduced into the wafer during formation processes, particularly metallic impurities, can have various adverse effects. For example, such impurities can cause increased leakage currents at barrier layers and capacitors in integrated circuits.
To address this problem, various methods, referred to as gettering methods, are known which attempt to remove impurities and other defects from the wafer and/or capture the impurities and defects. Extrinsic gettering techniques involve physically damaging a surface of the wafer, typically a rear surface, to create faults that become gettering sites, i.e., sites where the impurities are captured. An example of a known extrinsic gettering method involves bombarding the rear surface of a wafer with fine particles such as silicon. Intrinsic gettering, on the other hand, typically involves heat treating, i.e., annealing, in a cycle of high temperature, low temperature and medium temperature, in order to form and grow oxygen precipitates from the small amounts of bulk intrinsic oxygen present in the silicon. Such precipitates act as gettering sites. See, for example, U.S. Pat. Nos. 5,534,294 and 5,286,658.
However, anneal temperatures typically higher than 1,000° C. are required to grow precipitates from the intrinsic oxygen. As wafer technology continues to advance, and device structures on the wafer become denser, it is becoming necessary to avoid high temperature processing because high temperatures result in problems such as warping in these future generation wafers. The high temperatures needed in known intrinsic gettering methods are thus problematic.
Ion implantation is also known as a method of creating gettering sites in silicon wafers. For example, M. Follstaedt et al., “Formation of Cavities in Si and Their Chemisorption of Metals”, Inst. Phys. Conf. Ser. No. 146, pages 481-484 (1985) describes a method in which helium is implanted into a silicon semiconductive wafer at a typical dose of 1×10
17
He/cm
2
at 30 keV to form cavities in the wafer, followed by vacuum annealing at 700 to 900° C. to cause the He to permeate from the silicon and enlarge the cavities. Such cavities act as gettering sites.
J. Wong-Leung et al., “Diffusion and Trapping of Au to Cavities Induced by H-Implantation in Si”, Nucl. Instr. And Meth. In Phys. Res. B 106, pages 425-428 (1995) similarly describes the formation of cavities in a silicon wafer through the use of H implantation.
Rather than form cavities, other ion implantation techniques in which dislocation loops are found in the wafer and act as sinks for impurities are known. For example, J. Dziesiaty et al., “Improved Si-Epi-Wafers By Buried Damage Layer For Extrinsic Gettering”, 2nd International Autumn Meeting Proceedings: Gettering and Defect Engineering In Semiconductor Technology, pages 292-296 (1987), describes the use of ion implantation with non-doping elements such as Ar or Ne. These elements are implanted into the substrate, which is then annealed to annihilate the defects in the surface region while also growing the dislocation loops within the silicon substrate. Etching may be performed in order to remove the damage layer altogether in order to prevent redistribution of the contaminants in subsequent high temperature processing steps. T. Nagasaki et al., “Gettering Technique and Structure”, IBM Technical Disclosure Bulletin, vol. 17, no. 12, pages 3587-3588 (1975) also describes the use of Ar ion implantation.
Ion implantation with P and Si is also known. See, for example, G. Galvagno et al., “Al—O Interactions in Ion-Implanted Crystalline Silicon”, J. Appl. Phys., 76(4), pages 2070-2077 (1994). This reference indicates that a high temperature annealing step, on the order of 1,000 to 1,250° C., is required for nucleation and growth of gettering sites.
D. Weiner, “Oxygen Implantation For Internal Gettering and Reducing Carrier Lifetime”, Appl. Phys. Lett. 50(15), pages 986-988 (1987) describes the use of oxygen implantation in gettering. The method utilizes doses of oxygen in the range of 10
15
to 10
16
cm
−2
and an annealing temperature of 950° C. to produce buried defect gettering sites.
However, such ion implantation methods of gettering also suffer from several deficiencies. The significant defect formation can be clearly seen when the implantation doses exceed 10
16
cm
−2
. The defects consist of large dislocation loops and nanometer-size oxide precipitates which are insufficient to prevent the large dislocation loops from sliding to the surface of the wafer over time. This degrades and destroys the performance of integrated circuits manufactured from such wafers. Furthermore, oxygen implantation utilizing high doses is expensive and therefore commercially infeasible since the cost for an oxygen implantation increases proportionally with the oxygen implantation doses. The cost for an implantation that utilizes an oxygen dose of, for example, 10
16
cm
−2
would be 100 times higher than that which utilizes dose of 10
14
cm
−2
. Therefore, the maximum defect generation utilizing an implantation with the least amount of oxygen doses would be desirable.
Ion implantation is also known for other uses. For example, ion implantation has been used to introduce dopants into semiconductive wafers. See Schreutelkamp et al., “Pre-amorphization Damage in Ion-Implanted Silicon”, Materials Science Reports, pages 277-367 (1991). Oxygen implantation is used in SIMOX (Separation by Implanted Oxygen) methods, in which a buried layer of silicon dioxide is formed beneath the surface of a silicon wafer. See, for example, J. Jablonski et al., “Gettering Layer Formation in Low-Dose SIMOX Wafers”, Proceedings 1995 IEEE International SOI Conference, pages 34-35 (1995). As described in this reference, formation of the buried layer requires high temperature annealing.
What is desired is an intrinsic gettering technique that is effective in capturing impurities and point defects in a silicon wafer substrate, that does not require high temperature annealing steps, and that yields wafers in which the gettering sites remain stable over time.
SUMMARY OF THE INVENTION
It is an object of the present invention to develop an effective method of creating gettering sites in an epitaxial wafer. It is a further object of the present invention to develop a method of generating intrinsic gettering sites without any high temperature annealing steps. It is a still further object of the present invention to develop a method of gettering that achieves an epitaxial wafer in which metallic impurities have been gettered within the subsurface of the wafer substrate in dislocation loops, which dislocation loops remain stable and do not glide to the wafer surface over time.
These and other objects are achieved by a method of creating gettering sites in an epitaxial wafer, the method comprising
implanting silicon ions into a substrate of the wafer;
implanting oxygen ions into the substrate of the wafer;
thermally annealing the substrate of the wafer for a period of time sufficient to nucleate defects in the substrate; and
depositing an epitaxial layer upon a surface of the substrate, thereby forming gettering sites from the nucleated defects in the wafer.
The objects of the invention are also achieved by a semiconductive wafer comprising a substrate and an epitaxial layer on the substrate, wherein the substrate contains dislocation loops as gettering sites anchored by oxygen precipitate clusters so as to prevent the dislocation loops from sliding to the surface of the wafer over time.
REFERENCES:
patent: 4401506 (1
Ravi Jallepally
Tate Naoto
Wijaranakula Witawat
Coleman William David
Oliff & Berridg,e PLC
SEH America Inc.
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