Silicide uniformity for lateral bipolar transistors

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Lateral structure

Reexamination Certificate

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C257S122000, C257S557000, C257SE27079, C257SE29036, C438S134000

Reexamination Certificate

active

11027401

ABSTRACT:
Method and apparatus for forming a semiconductor device. The method includes defining a plurality of rows in a semiconductor layer. Thereafter, on one or more of the plurality of rows, one or more bipolar junction devices are formed. Each of the bipolar junction devices has a first end region and a second end region. A quantity of a pre-amorphization ion is then implanted into at least one of the first end region and the second end region of a bipolar junction device for example. A silicide is formed in the semiconductor layer at the first end region and the second end region having implanted therein the quantity of the pre-amorphization ion. Additionally, laterally extending upper edges of the plurality of rows forming corners may be rounded prior to the implantation of the pre-amorphization.

REFERENCES:
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patent: 6118171 (2000-09-01), Davies et al.
patent: 6767770 (2004-07-01), Horch et al.
patent: 2001/0054746 (2001-12-01), Yamada et al.
patent: 2002/0100918 (2002-08-01), Hsu et al.
S. Matsuda, et al., “Novel Corner Rounding Process for Shallow Trench Isolation utiling MSTS,” International Electron Devices Meeting Technical Digest, 1998, pp. 137-140.
Joo-Hyoung Lee et al., “A Study of Stress Induced p+
Salicided Junction Leakage Failure . . . ,” IEEE Transactions on Electron Devices, vol. 49, No. 11, pp. 1985-1992, 2002.

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