Silicide/metal floating gate process

Details Silicide/metal floating gate process Silicide/metal floating gate process

1990-07-09

1991-10-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 52, 437 60, 437192, 437195, 437200, 437919, H01L 2170

Patent

active

050574477

ABSTRACT:
The invention provides an integrated circuit capacitor with a silicided polysilicon electrode (which silicide has not been used as an etch stop) as a bottom plate and a metal layer as a top plate. Subsequent to the formation of a patterned polysilicon layer, a multilevel dielectric is formed, and a via is etched therethrough to a polysilicon capacitor bottom plate. Then the polysilicon bottom plate is clad with a refractory metal silicide. The capacitor dielectric is then deposited, such a dielectric preferably consisting of an oxide
itride layered dielectric. Contacts are etched to diffusion and to polysilicon electrodes as desired, and metal is deposited and patterned to form the top electrode of the capacitor over the capacitor dielectric, and to make contact as desired to diffusion and to polysilicon. This provides an improved silicide layer in the capacitor, as compared to processes which etch through oxide down to the silicide, and thus are using the silicide as an etch stop.

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