Silicide formation on polysilicon

Details Silicide formation on polysilicon Silicide formation on polysilicon

1991-08-26

1992-09-15

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437200, 437112, H01L 21283

Patent

active

051478200

ABSTRACT:
An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers. The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.

REFERENCES:
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 4631804 (1986-12-01), Roy
patent: 4742020 (1988-05-01), Roy
Wolf, S., et al., Silicon Processing for the VLSI Era Volume I-Process Technology, Lattice Press, 1986, pp. 386-399, 175-180.

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