Silicide contacts for CMOS devices

Details Silicide contacts for CMOS devices Silicide contacts for CMOS devices

1982-05-13

1984-10-09

Edlow, Martin H.

357 59, 357 42, 357 67, 357 231, H01L 2348, H01L 2904, H01L 2946, H01L 2978

Patent

active

044764820

ABSTRACT:
In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anisotropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

REFERENCES:
patent: 4313256 (1982-02-01), Widmann
patent: 4333099 (1982-06-01), Tanguay et al.
Rideout, V. L. IBM Tech. Disclosure Bull., vol. 23, No. 6, Nov. 1980, pp. 2563-2566, "Method of . . . Lines".

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