Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-01-08
2004-11-09
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S344000
Reexamination Certificate
active
06815797
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to anti-fuses and, more particularly, to a silicide bridged anti-fuse and a method of forming the anti-fuse with a tungsten plug metalization process.
2. Description of the Related Art
Trim elements are devices that are used in analog circuits to provide an electrically programmable method of adjusting certain device parameters. For example, trim elements are often used to trim resistor values in critical circuits. See Comer, “Zener Zap Anti-Fuse Trim in VLSI Circuits,” VLSI Design, 1996, Vol. 15, No. 1, p. 89.
One type of trim element is an anti-fuse. Unlike a fuse which, when programmed, changes from a low-resistance to a high-resistance device to block a current from flowing through the device, an anti-fuse is a device which, when programmed, changes from a high-resistance to a low-resistance device to allow a current to flow through the device.
FIG. 1
shows a cross-sectional view that illustrates a prior-art anti-fuse
100
. As shown in
FIG. 1
, anti-fuse
100
, which is formed in a n-type semiconductor material
110
, includes a p-well
112
that is formed in material
110
, and a n+ region
114
that is formed in p-well
112
. In addition, a metal interconnect
116
is formed on p-well
112
to make an electrical connection with p-well
112
, while a metal interconnect
118
is formed on n+ region
114
to make an electrical connection with n+ region
114
.
In operation, a first voltage is applied to p-well
112
via metal interconnect
116
, and a second higher voltage is applied to n+ region
114
via metal interconnect
118
. In this situation, the junction between p-well
112
and n+ region
114
is reverse biased, thereby allowing no current to flow from metal interconnect
116
to metal interconnect
118
.
To program anti-fuse
100
, the reverse biased voltage is increased until avalanche breakdown occurs at the p-n junction. The reverse biased voltage can be increased by, for example, increasing the voltage on n+ region
114
. When avalanche breakdown occurs, a breakdown current flows near the surface from metal interconnect
116
to metal interconnect
118
.
The current flow causes localized heating which, in turn, causes metal atoms from metal interconnect
118
to migrate to metal interconnect
116
along the path of the breakdown current. The metal atom migration results in a trace of metal being formed along the path of the breakdown current. The trace of metal provides a low-resistance path between metal interconnect
116
and metal interconnect
118
. (Prior art anti-fuses can also be programmed with forward-biased voltages that generate the necessary current flow.)
Although anti-fuse
100
performs satisfactorily, there is a need for alternate structures and methods of forming an anti-fuse.
SUMMARY OF THE INVENTION
The present invention provides a silicide bridged anti-fuse and a method of forming the anti-fuse. The silicide bridged anti-fuse can be fabricated in a tungsten plug metalization process that does not require any additional process steps to form the anti-fuse. As a result, anti-fuse trim elements can be added to an electrical circuit for no additional cost.
An anti-fuse in accordance with the present invention includes a well that is formed in a first semiconductor material. The first semiconductor material has a first conductivity type, while the well has a surface and a second conductivity type. The anti-fuse also includes a first doped region of the second conductivity type that is formed in the well, a second doped region of the first conductivity type that is formed in the well, and a third doped region of the second conductivity type that is formed in the well. The first and third doped regions have dopant concentrations that are greater than the dopant concentration of the well. The second doped region is spaced apart from the first doped region, and the third doped region is spaced apart from the first and second doped regions.
The anti-fuse further includes a layer of insulation material that is formed on the surface of the well. The layer of insulation material has a first opening that exposes the first doped region of the well, and a second opening that exposes the second doped region of the well. In addition, the layer of insulation material has a third opening that exposes the third doped region of the well.
In addition, the anti-fuse includes a first section of a second semiconductor material that is formed on the layer of insulation material and the first region, and a second section of the second semiconductor material that is formed on the layer of insulation material and the second region. The second section is spaced apart from the first section. Further, a first layer of dielectric material is formed on the first section, the second section, and the third doped region.
The present invention provides a method of forming an anti-fuse on a first semiconductor material of a first conductivity type. The method includes the steps of forming a well in the first semiconductor material, and forming a layer of insulation material on the surface of the well. The method also includes the step of removing a first portion of the layer of insulation material to expose a first region on the surface of the well, and a second portion of the layer of insulation material to expose a second region on the surface of the well.
In addition, the method includes the steps of forming a layer of second semiconductor material on the layer of insulation material, the first region, and the second region, and etching the layer of second semiconductor material to form a first section and a second section. Further, the method includes the step of removing the layer of insulation material between the first and second sections to expose a third region on the surface of the well.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 5525822 (1996-06-01), Vinal
patent: 5915179 (1999-06-01), Etou et al.
patent: 6404026 (2002-06-01), Tsuyuski
patent: 6563189 (2003-05-01), Dark et al.
P. Beaud et al., “0.5&mgr;m Technology Development and Qualification”, [online], [retrieved on Dec 14, 2003]. Retrieved from the internet: URL:http://legwww.epfl.ch/research/pdf/05umf.pdf>. pps. 1-2 (unnumbered).
Donald T. Comer, “Zener Zap Anti-Fuse Trim in VLSI Circuits”, VLSI Design, 1996, vol. 5, No. 1, pp. 89-100.
Coppock William M.
Dark Charles A.
Nilles Jeffery L.
Strachan Andy
Jackson Jerome
National Semiconductor Corporation
Nguyen Joseph
Pickering Mark C.
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