Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1996-12-18
2002-01-08
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S132000
Reexamination Certificate
active
06337507
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of integrated circuit devices and more particularly, to fusible link devices in semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
In integrated circuits including CMOS integrated circuits, it is often desirable to be able to permanently store information, or to form permanent connections on the integrated circuit after it is manufactured. Fuses or devices forming fusible links are frequently used for this purpose. Fuses can be used to program redundant elements to replace identical defective elements, for example. Fuses can also be used to store die identification or other such information, or to adjust the speed of a circuit by adjusting the resistance of the current path.
In some cases, electrically erasable programmable read only memory (EEPROM) devices are used to perform the discretionary connection function of a fuse device. Semiconductor process technologies continue to provide for smaller device geometries and operate at lower voltages. As the device geometries are reduced, so is the thickness of the gate oxide layer. EEPROM memory devices require a minimum gate oxide thickness to prevent high leakage currents and sustain a charge on the floating node. Thus, EEPROM memory devices are not viable for use on many of the latest semiconductor process technologies.
Other fuse devices require an extra semiconductor processing step to form or program the discretionary connections. For example, one type of fuse device is “programmed” using a laser to open a link after the semiconductor device is processed. This type of fuse device not only requires an extra processing step to program or “blow” the fuse devices where desired, but also requires precise alignment of the laser on the fuse device to avoid destroying neighboring devices. This and other similar approaches can result in damage to the device passivation layer, and thus, lead to reliability concerns. In some approaches, the passivation layer must actually be removed before programming the fuse device to provide space for the fuse material when the connection is destroyed. In other approaches, where the passivation layer is not intentionally removed, the process of blowing the fuse can cause a hole in the passivation layer when the fuse material is displaced.
Another type of memory device, referred to as an “oxide antifuse” device, is programmed using high voltages compared to the circuit's normal operating voltage supply. Therefore, the peripheral circuitry for these devices generally requires higher junction breakdown voltages than those normally available on the integrated circuit. This is an issue for newer process technologies and those in development for the same reasons described above in reference to EEPROM memory devices. The reduced gate oxide thicknesses require higher well doping which results in lower junction breakdown voltages, and thus, oxide antifuse devices may also not be viable for use with many of the latest process technologies.
The invention provides a small fuse device which can be manufactured without additional processing steps, and which can be reliably used with lower voltage, thinner gate oxide process technologies in use today and in development for the future. Further, the fuse device of the invention can be programmed using relatively low voltages without damage to overlying dielectric layers.
SUMMARY OF THE INVENTION
A fusible link device disposed on a semiconductor substrate for providing discretionary changes in resistance is described. The fusible link device of the invention includes a polysilicon layer having a first resistance and a silicide layer formed on the polysilicon layer having a second, lower resistance. The silicide layer includes a fuse region having a first notched region narrower than the center of the fuse region, a first contact region coupled to one end of the fuse region, and a second contact region coupled to an opposite end of the fuse region. The silicide layer is agglomerable to form an electrical discontinuity in the fuse region in response to a first current greater than or equal to a predetermined programming current flowing through the fuse such that the resistance of the fusible link device can be selectively increased.
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“Polysilicon Fuse Structure”,IBM Technical Disclosure Bulletin, vol. 29, No. 1, (Jun. 1986) pp 144-145.
Alavi Mohsen
Bohr Mark T.
Tsai Min-Chun
Crane Sara
Faatz Cynthia T.
Intel Corporation
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