Fishing – trapping – and vermin destroying
Patent
1995-06-07
1997-12-16
Niebling, John
Fishing, trapping, and vermin destroying
437192, 437228ES, H01L 2144
Patent
active
056984685
ABSTRACT:
A semiconductor processing method forms etch stop layers over semiconductor structures without the need for additional etching, masking, and deposition steps. A refractory metal capable of forming silicides and oxides under standard processing conditions is deposited over the deposition, oxide, and polysilicon layers of a MOS integrated circuit wafer. The coated wafer is first annealed to form refractory metal silicide layers over the unoxidized silicon structures. The coated wafer is then oxidized to convert unreacted refractory metal over the oxidized silicon structures into refractory metal oxide etch stops over these structures.
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Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattice Press, pp. 144-147, 1990.
LSI Logic Corporation
Niebling John
Turner Kevin F.
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