Signed overflow sticky bits

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G06F 738

Patent

active

053195884

ABSTRACT:
An arithmetic unit for multiplying and accumulating signed binary data and indicating an occurrence of a signed arithmetic overflow includes a multiplier-accumulator and an overflow flag register. The multiplier-accumulator receives and selectively multiples and accumulates signed binary data, and provides output data representing the multiplied and accumulated data and a sign bit representing its polarity, i.e. positive or negative. The flag register provides two "sticky" flag bits for indicating whether a signed arithmetic overflow (positive or negative) of the multiplied and accumulated data has occurred. The flag bits are "sticky" in that once a flag has been set, it cannot be reset by another arithmetic overflow condition. Instead, it must be specifically reset. The sign bit is used to selectively set one of the two sticky flag bits to a true state to indicate the direction (positive or negative) of the first arithmetic overflow. The sticky flag bits have mutually exclusive true states in that once a flag bit has been set true, the other flag bit cannot be set true until both flag bits have been specifically reset.

REFERENCES:
patent: 4534010 (1985-08-01), Kobayashi et al.
patent: 4722066 (1988-01-01), Armer et al.
patent: 4945507 (1990-07-01), Ishida et al.
patent: 5038313 (1991-08-01), Kojima
patent: 5138570 (1992-08-01), Argade
patent: 5150319 (1992-09-01), Zyner

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