Signed multiplier with three port adder and automatic adjustment

Details Signed multiplier with three port adder and automatic adjustment Signed multiplier with three port adder and automatic adjustment

1986-07-11

1988-08-02

Malzahn, David H.

Boots, shoes, and leggings

364760, G06F 752

Patent

active

047617560

ABSTRACT:
Disclosed is a signed multiplier for use in a data processing system that handles 2's complement operands. The signed multiplier operates to form a preliminary product independently of the signs of the multiplier and multiplicand. While the multiplication is in progress, the signs of the multiplier and multiplicand are checked. For multiplications where either one of the operands (multiplier or multiplicand) is negative, the preliminary product is modified by one or two correction factors. The correction factors are multiplies of the 2's complements of the operands. The correction factor or factors are added to the preliminary product to form the final product.

REFERENCES:
patent: 3627999 (1971-12-01), Iverson
patent: 3761699 (1973-09-01), Sather
patent: 3866030 (1975-02-01), Baugh et al.
patent: 4086474 (1978-04-01), Negi et al.
patent: 4467444 (1984-08-01), Harmon, Jr. et al.
patent: 4507749 (1985-03-01), Ohhashi
Capps et al., "Two's Complement Multiplication", IBM Tech. Disclosure Bulletin, vol. 20, No. 12, May 1978, pp. 5292-5293.
Davby et al., "Two's Complement Multiplier", IBM Tech. Disclosure Bulletin, vol. 18, No. 5, Oct. 1975, pp. 1482-1483.
Robertson, "Two's Complement Multiplication in Binary Parallel Digital Computers", IRE-Trans.-Electronic Computers, Sep. 1955, pp. 118-119.

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