Signed multiplication logic

Details Signed multiplication logic Signed multiplication logic

1974-11-22

1976-03-30

Dildine, Jr., R. Stephen

Registers

Transfer mechanism

Traveling pawl

235156, G06F 739

Patent

active

039476707

ABSTRACT:
The present invention relates to signed multiplication logic for multiplying two serial binary numbers to obtain a serial binary product, the multiplicand containing magnitude and sign information in two's complement notation, the multiplier containing magnitude information, and the product containing magnitude and sign information in two's complement notation, all three bit streams occurring serially at equal word rates with the least significant bit first in time. The logic is composed of a plurality of largely identical multiplication cells which form partial products which are summed in largely identical summation cells to form the final product. Each multiplication cell stores a multiplier bit, contains a stage of a multiplicand shift register and a stage of a timing waveform shift register. Means are provided for truncation of the multiplicand and product rounding under timing waveform control. The logic is flexible and may be used to form single or double precision products. The design in utilizing two largely identical cells, with a minimum of communication paths at the cell and multiplication logic boundaries, is optimized for large scale integration using metal oxide semiconductor field effect transistor technology.

REFERENCES:
patent: 3617723 (1971-11-01), Melvin
patent: 3800130 (1974-03-01), Martinson et al.

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