Signature analysis technique for defect characterization of CMOS

Details Signature analysis technique for defect characterization of CMOS Signature analysis technique for defect characterization of CMOS

1987-11-09

1989-05-30

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

324158R, 324 73AT, 371 21, 365201, G01R 1512, G11C 1140, G06F 1126

Patent

active

048354589

ABSTRACT:
An error testing process for the testing of CMOS static RAM memories. Individual static RAM memory cells that have failed are isolated. A typical cell has six transistors, two access, two n-channel and two p-channel. The access transistors are allowed to float which effectively isolates the cell. By application of voltages to the n-channel or p-channel transistors one set can be turned off and the remaining two n-channel or p-channel transistors can be tested with microprobes varying voltages for the forward and reverse bias testing. The graphs of the current flow from these tests are compared using the signature analysis technique so that not only the exact transistor which failed can be identified but the failure mechanism can also be identified. This process permits error testing without damage to the RAM memory and without physical isolation of the SRAM memory.

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