Boots – shoes – and leggings
Patent
1981-12-28
1985-04-09
Wise, Edward J.
Boots, shoes, and leggings
371 25, 324 73AT, 324 73R, G06F 1100, G01R 3128
Patent
active
045105723
ABSTRACT:
A signature analyzer for testing digital circuits. The analyzer includes a memory which is initially programmed with a set of signatures characterizing the digital signals on the nodes of a correctly operating circuit. The nodes of a test circuit are then sequentially applied to a signature generator formed by a multi-stage shift register having the outputs of selected stages fed back to a gate to which the digital signal is applied. The signature generated by the shift register is compared to each of the signatures stored in memory until a signature match is found, thus indicating that the digital circuit, at least as far as the test node is concerned, is operating correctly. The signature generated by the shift register consists of twenty-four bits to provide a probability of error which is comparable to the probability of error in comparing a sixteen-bit signature with the signature from a specifically identified node. At the conclusion of a gate period, sixteen bits of the signature are displayed as four hexedecimal digits. In order to minimize the probability of error, the analyzer also counts the number of transitions of the digital signal during the gate period and compares the count to transition counts stored in memory for the digital signals on the nodes of a correctly operating circuit. A comparison is then made of the transition count at the test node with each of the transition counts stored in memory. The analyzer thus ensures a transition count match as well as a signature match.
REFERENCES:
patent: 3976864 (1976-08-01), Gordon et al.
patent: 4194113 (1980-03-01), Fulks et al.
patent: 4348760 (1982-09-01), Rice et al.
Transition Count Testing of Combinational Logic Circuits, J. P. Hayes, IEEE Transactions on Computers, Vo. C.25, No. 6, Jun. 1976, pp. 613-620.
Testing a Microprocessor Product Using Signature Analysis, H. J. Nadig, Conference 1978 Semiconductor Test Conference, Cherry Hill, N.J., Oct.-Nov. 1978, pp. 159-169.
Logic-State and Signature Analysis Combine for Fast, Easy Testing, I. H. Spector, Electronics/Jun. 8, 1978, vol. 51, No. 12, pp. 141-145.
Retrofitting for Signature Analysis Simplified, R. Rhodes-Burke, Hewlett-Packard Journal, Jan. 1982, vol. 33, No. 1, pp. 9-16.
Franzel John R.
Martin Robert G.
Reece John M.
Data I/O Corporation
Wise Edward J.
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