Pulse or digital communications – Cable systems and components
Reexamination Certificate
2000-08-08
2004-11-23
Chin, Stephen (Department: 2634)
Pulse or digital communications
Cable systems and components
C375S224000
Reexamination Certificate
active
06823020
ABSTRACT:
FIELD OF THE INVENTION
The invention concerns a signalling output stage for generating digital voltage signals on a bus system connecting a central processor unit via two signal lines to a plurality of modules.
BACKGROUND INFORMATION
According to the state of the art, so-called push-pull-signalling output stages with two sets of transistor-switching equipment are usually used as signalling output stages, connecting a line either with the supply voltage or to ground. In general, short circuits to an interference potential (e.g. to ground), the supply voltage, or another third potential may lead to an attenuation of the necessary :signal amplitude and thus to faults in the signal recognition up to and including the failure of the signalling output stage.
In order to prevent this, an integrated transmit and receive circuit is to be taken from DE 196 11 944 A1 for coupling a control unit to a two-wire bus, where a test device for fault recognition on the bus system lines is provided and where, in addition to a standard operating mode, further different operating modes are provided which, in the event of a fault, allow communication adjusted to the actual fault type. This is known as a fault-related change-over of the circuit termination elements. Employing the switching equipments in
FIG. 3
a
makes it possible, if signal reception is no longer possible with VCC, to initially apply CAN_L to Vbatt, instead of using termination resistors
16
and
17
which in normal operation mode apply CAN_H to GND and CAN_L to VCC. Moreover, it is also possible to deploy very low current sources
26
and
27
permitting a current-limited retention of the signal reception. Column 7, starting at line
56
, indicates that in the event of a defect, signalling can be abandoned as the transmission signal TXD can no longer have any effect on the bus. The change-over thus mainly affects the reception of signals in a faulty bus, but not their transmission.
DE 39 01 589 A1 describes the coupling-up of a bus participant, in which a resistor network assures that even in the presence of faults on the bus lines the data existing on the data bus can always be recognized. Here again, only those faults which occur during reception, and not at the time of transmission, are being considered, even though transmission outputs are also connected by means of this resistor network, but being connected in a rigid way and consequentially not adaptable to the fault type.
DE 195 09 133 A1 also describes a reception device compensating bus faults, that changes between one- and two-wire reception.
Therefore, these publications may suggest the various fault types, particularly short circuits to supply voltages or ground potential, but they do not consider a signal generation adapted thereto.
DE 44 03 899 A1 teaches such a generic signalling output stage in a device for serial data transmission between at least two stations. Thus,
FIG. 2
shows a signalling output stage where an upper switching equipment or device (T
2
) is connected between a first voltage potential (V
2
) and a first line (S+), and a lower switching equipment or device (T
3
) is connected between a second voltage potential (ground) and the second line (S−). In addition to this, various operating modes are provided for the case of a fault on one of the lines, which enable a signal generation adapted to the type of the fault. Checking the lines for short circuits, and signalling control, are implemented by direct technical switching or circuit means, that is, shifting voltage potentials on the lines will directly lead to different electrical conditions and thus to a different signalling. Thus, an independent signalling is provided for on both lines S+ and S−, that is, line S+ is not only connectable to V
2
via R
5
,T
2
, but it can also be permanently grounded, via the high ohmic resistance R
7
, while S−, via R
4
, highly ohmically quiescently rests at V
2
and can be pulled to ground by switching T
3
.
In any emergency, signalling can thus be performed both just via S+ on its own as well as via S− on its own. In normal operation mode, both lines feature straight inverse signals to one other (compare
FIG. 4
a
). In addition, both lines feature a quiescent potential.
In correspondence to this, DE 195 03 460 C1 also describes a failure tolerant output stage of the generic type which features a test device (condition detection module) designed for the detection of faults and their particular type, as well as a transmission module with different operating modes, where again, however, the first and second line of the bus system can signal independently of one another, because both lines each have their own connection to a high and a low voltage potential, as can be seen from FIG.
2
.
SUMMARY OF THE INVENTION
Based on this state of the art, this invention has the task to describe a further bus failure-tolerant signalling output stage, that does not have a fixed quiescent current load and yet provides a simple way, at least for the majority of possible faults, to continue signal generation in a different operating mode. Additionally, a particularly preferred application within a bus system is to be stated, where the certainty of data transmission being maintained, even in the event of any faults occurring on the bus system, will be further improved.
The above stated task is achieved according to the invention in a signalling output stage for the generation of digital voltage signals on a bus system with a central processor unit and a number of modules, connected to it by means of two lines, where the digital voltage signals assume one high voltage level and a corresponding lower voltage level. An upper switching equipment between a first voltage potential and the first line, as well as a lower switching equipment between a second, comparatively lower voltage potential and the second line are provided for. The central processor unit features a test device, by means of which faults on the lines, particularly short-circuits to a voltage potential can be detected. A standard operating mode is provided, in which signal generation is effected by the high voltage level being generated by closing the upper and lower switching equipments, and the low voltage level by opening at least the upper switching equipment. In case of a fault, additional different operating modes are provided for, which in spite of the fault enable digital voltage signals to be generated in such a way that they are adjusted to the type of fault. Further, a middle switching equipment is provided between the first line and the second line, by means of which signal generation will be maintained at least in the case of a fault on one line.
The above stated task is further achieved according to the invention in a circuit arrangement including the inventive signalling output stage, within a bus system, and further comprising the following features. All of the modules are further furnished with at least one short-circuit testing device for the two lines. The testing device is adapted to check the output of the respective line for an effective short-circuit, namely an effective resistance which is too low. For each of the two lines, there is further provided one switching device located between an input and an output of the respective line. The switching devices are respectively adapted to switch a connection between the input and the output of each respective one of the two lines, only after a test has been executed at the respective output by means of the respective short-circuit testing device and if the test has proven the absence of a short-circuit.
Advantageous further developments and embodiments of the invention are as set forth in the claims following this written description.
By using the two lines and three sets of switching equipment, it will become possible to drive the modules jointly via both lines, or individually, via only one of the lines, if a fixed interference potential is being applied to the other line. Both lines can assume either of the
Bauer Joachim
Bischoff Michael
Fendt Guenter
Karl Otto
Mueller Norbert
Chin Stephen
Conti Temic microelectronic GmbH
Fasse W. F.
Fasse W. G.
Perilla Jason M.
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