Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-11-01
2003-09-02
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S055000, C327S089000
Reexamination Certificate
active
06614272
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to signal voltage detection circuit having a differential amplifier for detecting an input signal voltage and a latch circuit for holding therein a detection result.
2. Description of Related Art
In driver integrated circuits (ICs) for driving power switching devices including, but not limited to, metal oxide semiconductor (MOS) transistors and insulated gate bipolar transistors (IGBTs), signal voltage detection circuitry is used for error detection and the like, by way of example.
FIG. 13
is an exemplary configuration of one prior known signal voltage detection circuit
10
of the type stated above. A differential amplifier
11
has a pair of driver transistors N
1
, N
2
, to which a reference voltage Vref and a signal voltage Vin to be detected are input respectively. In order to take out or derive an output current which corresponds to a detection output of this differential amplifier
11
, a current mirror circuit
12
is provided. A change in output current of the current mirror circuit
12
is detected by a current-to-voltage conversion circuit
13
, which includes a resistor R
1
and a transistor MN
1
for detection of its terminal voltage. An output of this current-voltage conversion circuit
13
is transferred via an inverter X
1
toward a latch circuit
14
and is then held therein.
FIG. 14
is an operation timing diagram of the signal voltage detector circuit
10
. When the input signal voltage Vin becomes higher in potential than the reference voltage Vref (at a time point t
0
), a collector current of the driver transistor N
2
of the differential amplifier
11
changes from zero to a constant current. Upon receipt of the detection output of this differential amplifier
11
, a drain current flows in P-channel MOS transistors MP
1
, MP
2
which make up a current mirror circuit
12
. In responding to receipt of an output voltage of the MOS transistor MP
2
, a voltage generates across the both terminate ends of the resistor R
1
whereby the N-channel MOS transistor MN
1
turns on. Thus, the input level of the inverter X
1
potentially drops down at “Low” or “L” level, permitting a pulse of “High” or “H” level—say, H pulse—to be input to the latch circuit
14
, resulting in retention of a latch output which is represented by Vout=L.
Even when the signal voltage Vin becomes potentially lower than the reference voltage Vref (at a time point t
1
), the data held in the latch circuit
14
is kept unchanged. The latch circuit
14
's hold data will be reset in response to a potential change of a reset signal RST to H level (at t
2
).
FIG. 15
shows another signal voltage detection circuit
20
. This circuit includes its differential amplifier
21
, which has an NPN transistor N
1
to which the reference voltage Vref is input and a parallel combination of NPN transistors N
21
, N
22
to which two signal voltages Vin
1
, Vin
2
are input respectively. These driver transistors are operatively associated with a load, which is an active load. More specifically, PNP transistors P
1
, P
2
for use as the load are connected to make up a current mirror circuit. The differential amplifier
21
generates a detection output, which is amplified by a voltage amplifying unit
22
with large-amplitude operability and is then sent forth via inverters X
1
, X
2
to a latch circuit
23
and held therein.
FIG. 16
is an operation timing diagram of this signal voltage detector circuit
20
. When either one of the input signal voltages Vinl, Vin
2
becomes higher in potential than the reference voltage Vref (at time point t
0
), the collector current of a corresponding one of the driver transistors N
21
, N
22
of the differential amplifier
21
changes from zero to a constant current. Upon receipt of this change, a PNP transistor P
3
turns on causing the collector current to flow therein, resulting in an H pulse being obtained at a terminal of resistor R
1
. Whereby, a voltage of Vout=L is latched in the latch circuit
23
.
Even when the signal voltage Vin potentially decreases below the reference voltage Vref (at time point t
1
), the data held at the latch circuit
23
is kept unchanged. The latch circuit
23
's hold data will be reset in response to a potential change of the reset signal RST to H level (at t
2
).
The signal voltage detector circuits
10
and
20
of
FIGS. 13 and 15
are both associated with risks of operation failures or malfunction occurring due to the influence of power supply noises. A timing diagram of the signal voltage detector circuit
10
of
FIG. 13
in the case of occurrence of such malfunction is shown in
FIG. 17
; a timing diagram of the
FIG. 15
detector circuit
20
in a similar case is shown in FIG.
18
.
Firstly, in the signal voltage detector circuit
10
of
FIG. 13
, suppose that the power supply voltage Vcc potentially drops down by a certain degree &Dgr;V at a time point t
10
as shown in FIG.
17
. In response to receipt of this potential drop-down, the current of a current source I
1
of the differential amplifier
11
also decreases accordingly. And, when the power supply voltage initiates to recover at a time point t
11
, a displacement current rushes to flow in a relatively large collector capacitance of the driver transistor N
2
. This in turn causes a drain current to flow in the P-channel MOS transistors MP
1
, MP
2
of the current mirror circuit
12
. Owing to the current of MOS transistor MP
2
, the terminal voltage of resistor R
1
increases in potential. When this voltage goes beyond the threshold voltage of NMOS transistor MN
1
, this MOS transistor MN
1
turns on resulting in the voltage Vout=L of latch circuit
14
being latched unintentionally.
In the signal voltage detector circuit
20
of
FIG. 15
, assume that the power supply voltage Vcc potentially decreases by &Dgr;V at time point t
10
as shown in FIG.
18
. In this case, the current of current source I
1
of the differential amplifier
21
also decreases. Simultaneously, the PNP transistors P
1
, which make up the current mirror with the PNP transistor P
2
and is flowing a constant current, also decreases in collector current thereof. Upon potential recovery of the power supply voltage from time point t
11
, the collector current of one load transistor P
1
recovers up to the constant current while including a displacement current for charge-up of the collector capacitance of driver transistor N
1
. At the other load transistor P
2
, a collector current flows therein as a displacement current used to charge up the large collector capacitance of driver transistors N
21
, N
22
, causing a base current of the transistor P
3
to be pulled out of it. In responding thereto, an H pulse generates at the terminal of resistor R
1
and is then supplied to the latch circuit
23
. This would result in the voltage Vout=L being latched in latch circuit
23
, although not specifically required.
As previously stated, the signal voltage detector circuit of
FIG. 13
or
15
is encountered with the risk of unwanted occurrence of operation errors or malfunction due to power noises because of the presence of the collector capacitance of more than one driver transistor used. The driver-transistor collector capacitance stays harmless with respect to ordinary or standard signal detection operations. However, in the event that the power supply voltage recovers to its normally expected potential level once after rapid or “spike”-like drop-down due to externally attendant noises or else, the displacement current for chargeup of the collector capacitance flows in accordance with a potential change of the supply voltage without regard to the absence of any input to the differential amplifier. This displacement current flow can cause malfunction.
More practically, the circuit of
FIG. 13
is faced with a problem as to the inequality or “imbalance” of parasitic capacitances associated with the drain side of P-channel MOS transistors MP
1
, MP
2
making up the current mirror circuit
12
. Whe
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Toan
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