Pulse or digital communications – Cable systems and components
Reexamination Certificate
2002-02-19
2002-12-10
Pham, Chi (Department: 2631)
Pulse or digital communications
Cable systems and components
C365S198000, C326S020000
Reexamination Certificate
active
06493394
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal transmission system and a receiver circuit for use in the signal transmission system, and more particularly, to a signal transmission system for transmitting signals between LSI chips and a receiver circuit for use in the same.
2. Description of the Related Art
Recently, DRAM (Dynamic Random Access Memory) and processor performances have improved dramatically, and more specifically, processor performance has improved rapidly in terms of speed, while the improvement of DRAM performance has been dramatic primarily in terms of storage capacity. However, the improvement in operating speed of DRAM has not been so dramatic as the increase in storage capacity, as a result of which the speed gap between DRAM and processor has widened and this speed gap has become a bottleneck in boosting computer performance in recent years.
Among the signal transmission systems for signal transmission between processors and DRAMs (DRAM modules) known in the prior art and expected to find widespread use in the next few years are the SSTL (Series-Stub Terminated Logic) and other low-amplitude signaling standards. In the SSTL (or in a similar low-amplitude signaling system), a signal transmission line (hereinafter the transmission line) is terminated in a resistance close to the characteristic impedance of the transmission line, thereby suppressing reflections at its terminating ends and achieving high signal transmission speeds. Furthermore, by using low-amplitude signaling, the power required to charge and discharge the transmission line is reduced, making low-power transmission possible in high-speed operation.
In a bus system (signal transmission system) employing the SSTL, high-speed signal transmission is made possible because of matched termination (terminal resistance) and stub resistance, and power consumption also is reduced compared to traditional systems because of the use of low-amplitude signaling. However, in order to maintain the overall power consumption of the apparatus at the current level, or reduce it below the current level, while increasing the signal transmission bandwidth between DRAM and processor, a signal transmission system with lower power consumption is demanded.
Further, for example, in a Rambus channel, a DRAM controller and a plurality of DRAM chips are interconnected by a common signal transmission line (bus). For transmission and reception of high-speed signals, precise timing must be established between the signal sender and receiver. In the Rambus channel, correct timing can be established for both reception and transmission, provided that a clock line and a signal transmission line are identical both in routing and in electrical characteristics. That is, the Rambus channel requires that the clock line and the signal transmission line be formed along the same route and have the same electrical characteristics between them.
However, the characteristic of the load is inevitably different between the clock line and the signal transmission line. This is because, while the signal transmission line permits the use of a latch circuit operating in synchronism with receive timing to achieve high-sensitivity reception, the clock line requires the use of a differential amplifier, etc. since a latch cannot be used. Since the nature of the load is different between a latch circuit and a differential amplifier and the like, line electrical characteristics (for example, delay per unit distance), etc. are bound to become different between the clock line and the signal transmission line.
The prior and related arts, and their associated problems will be described in detailed later with reference to the accompanying drawings
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a signal transmission system wherein the response time of a signal transmission line is set approximately equal to or longer than the length of a transmitted symbol. It is another object of the present invention to provide a signal transmission system that can generate timing signals without demanding symmetry between the clock line and the signal transmission line (bus), and that can minimize the gap when switching is made from one transmitting device to another.
According to the present invention, there is provided a signal transmission system wherein the response time of a signal transmission line is set approximately equal to or longer than the length of a transmitted symbol.
A terminal resistance provided at one or both ends of the signal transmission line may be set larger than a characteristic impedance of the signal transmission line. At least one resistor may be provided in series with the signal transmission line or the signal transmission line may be constructed to contain resistance in itself.
Signals may be transmitted between a plurality of circuit blocks. At least one of the plurality of circuit blocks may have a receiver circuit for receiving a signal transmitted out on the signal transmission line, and the receiver circuit may comprise a partial-response detection unit for detecting a partial response that the signal shows, and a signal logic decision unit for making a logic decision on the signal. The partial-response detection unit may comprise an intersymbol interference estimation unit for estimating intersymbol interference based on a previously received signal and a subtracting unit for subtracting the estimated intersymbol interference from a signal in effect currently received.
The intersymbol interference estimation unit may be constructed to obtain a sum of linear weights of previous decision values. The intersymbol interference estimation unit may comprise a shift register for holding previous bit information and a weighting unit for weighting data held in the shift register. The weighting unit may be constructed from a plurality of resistors. The weighting unit may be constructed from a plurality of capacitors and switches.
The intersymbol interference estimation unit may be constructed to obtain nonlinear weights of previous decision values. The intersymbol interference estimation unit may comprise a shift register for holding previous bit information and a memory unit for storing estimates corresponding to data held in the shift register.
The intersymbol interference estimation unit may comprise an accumulating unit for accumulating an analog value of the previously received signal and an intersymbol interference generating unit for generating intersymbol interference from the analog value. The intersymbol interference estimation unit may be constructed to take a linear weighted sum of an analog value of a signal received one clock back and a fixed reference analog value. The intersymbol interference estimation unit may be provided with a plurality of switch units and capacitor units.
The plurality of circuit blocks may be semiconductor integrated circuit chips, and the signal transmission system may be configured as a bus system interconnecting the plurality of semiconductor integrated circuit chips. The signal transmission line may be configured as a bidirectional data bus or data signal line. The signal transmission line may be configured as a unidirectional address bus or address signal line. The plurality of semiconductor integrated circuit chips may be constructed with a processor or controller and a plurality of memory modules.
Further, according to the present invention, there is provided a signal transmission system for transmitting a signal between a plurality of circuit blocks via a signal transmission line, comprising a clock distribution unit for distributing a clock to each of the circuit blocks via a clock line; a common timing signal generating unit for providing common timing based on the clock to each of the circuit blocks with an accuracy of time shorter than the time required for the signal to travel through wiring between the circuit blocks; and a unit for transmitting and receiving the signal in synchronism with the common timing.
Each of th
Araki Hisakatsu
Cheung Tsz-shing
Gotoh Kohtaroh
Ogawa Junji
Saito Miyoshi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Tran Khai
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