Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-03-07
2004-04-20
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S391000, C326S081000
Reexamination Certificate
active
06724226
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more particularly, to an input buffer capable of tolerating high input voltage.
2. Description of the Related Art
In general, an input buffer responds to a signal having a predetermined voltage level, e.g., a transistor—transistor logic (TTL) signal, converts the signal into a signal having a predetermined different voltage level, e.g., a complementary metal oxide semiconductor (CMOS) signal, and supplies the converted signal to an internal circuit of an integrated circuit (IC). An input buffer is connected to an input pad of an IC.
A signal externally applied to the input pad of an IC may not be a signal that is appropriate for normal operation of the IC. In a case where an external device electrically connected to an input pad of an IC having a voltage higher than a supply voltage used in the IC, the input buffer must also operate with a voltage higher than the supply voltage used in the IC.
In a case where a supply voltage of 5V, 3.3V, 2.5V and 1.8V is supplied to an IC, a buffer which is driven by an input signal having a voltage higher than the supply voltage of the IC is referred to as a tolerant input buffer.
In general, in a case where a supply voltage of 3.3V, or 2.5V is used, the highest tolerable input signal is 5V. In a case where a supply voltage of 1.8V is used, a highest tolerable input signal is 3.3V.
FIG. 1
illustrates a conventional tolerant input buffer circuit. Referring to
FIG. 1
, the tolerant input buffer includes a pad
1
, a resistor R
1
, a path transistor T
1
, a Schmitt trigger
3
, and an inverter
5
. An input signal IN is input to the pad
1
, and the resistor R
1
restricts current flowing to the drain of the path transistor T
1
.
The pass transistor T
1
is implemented by a NMOS transistor and transmits a signal smaller than a supply voltage Vdd
1
for the input signal IN greater than the supply voltage Vdd
1
(e.g., 3.3V) applied to the gate to a node n
1
. That is, in a case where the input signal IN is greater than the supply voltage Vdd
1
, the path transistor T
1
transmits a signal whose voltage is lowered to a threshold voltage (hereinafter referred to as ‘Vth’) of the NMOS transistor from the supply voltage Vdd
1
, to the node n
1
.
The path transistor T
1
may cut off at a voltage lower than an input logic high voltage (VIH) of the Schmitt trigger
3
due to the threshold voltage Vth increased by a body effect. As a result, when designing a VIH, in the worst case, the node n
1
becomes a floating node, and thus, the input buffer is driven by a voltage generated by leakage current in a sub-threshold region, and the VIH is indicated as a higher value, thereby affecting sizing of the input buffer.
For example, if the input signal IN is linearly increased from 0V to 3.3V at the pad
1
, an ideal tolerant input buffer of 5V must transmit the signal of 0V~3.3V to the node n
1
. However, referring to
FIGS. 4 and 5
, the conventional tolerant input buffer is cut off by the threshold voltage of the path transistor T
1
at the point of 2.2V, and thus, a DC/AC voltage Vn
1
transmitted to the node n
1
gradually increases from the point of 2.2V and loses its linearity. This problem occurs in an analog tolerant input circuit such as a comparator and an amplifier.
Further, since the path transistor T
1
is cut off before the VIH of the Schmitt trigger
3
, the input voltage of the Schmitt trigger
3
is increased by leakage current of the path transistor T
1
until reaching a transition voltage of the Schmitt trigger
3
, and thus, it takes a long time to reach the transition voltage of the Schmitt trigger
3
. As a result, propagation delay increases.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a signal transmission circuit that is capable of improving DC characteristics, delay characteristics, and linearity in a voltage region and of maintaining tolerant functions.
According to an embodiment of the present invention, there is provided a signal transmission circuit. The signal transmission circuit includes a first transmission circuit for transmitting a signal of a first node to a second node, a second transmission circuit for transmitting the signal of the first node to the second node, an inverting circuit for inverting the signal of the second node, a first switching circuit for pulling down a third node in response to an output signal of the inverting circuit, and a second switching circuit for transmitting the signal of the first node to the third node. The second transmission circuit is controlled in response to the signal of the third node.
According to another embodiment of the present invention, there is provided a signal transmission circuit. The signal transmission circuit includes a first transmission circuit for transmitting a signal of a first node to a second node, a second transmission circuit for transmitting the signal of the first node to the second node, a transition control circuit for controlling transition from a first state to a second state, or from the second state to the first state, in response to an output signal of the second node, a first switching circuit for pulling down a third node in response to an output signal of the transition control circuit, and a second switching circuit for transmitting the signal of the first node to the third node. The second transmission circuit is controlled in response to the signal of the third node.
In one embodiment, the first transmission circuit is an NMOS transistor, a first supply voltage is input to the gate of the NMOS transistor, a first end of the NMOS transistor is connected to the first node, and a second end of the NMOS transistor is connected to the second node. The second transmission circuit can be a PMOS transistor, a gate of the PMOS transistor being connected to the third node, a first end of the PMOS transistor being connected to the first node, and a second end of the PMOS transistor being connected to the second node.
The first switching circuit can include an NMOS transistor, an output signal of the inverting circuit can be input to the gate of the NMOS transistor, a first end of the NMOS transistor being connected to the ground voltage, and a second end of the NMOS transistor being connected to the third node. The second switching circuit can be a PMOS transistor, a second supply voltage can be input to the gate of the PMOS transistor, a first end of the PMOS transistor can be connected to the first node, and a second end of the PMOS transistor can be connected to the third node.
Preferably, the second supply voltage is generated in a voltage generation circuit, and the first supply voltage is greater than the second supply voltage, the inverting circuit is a Schmitt trigger, and the signal transmission circuit is a tolerant input buffer.
REFERENCES:
patent: 5576635 (1996-11-01), Partovi et al.
patent: 5892377 (1999-04-01), Johnston et al.
patent: 6057717 (2000-05-01), Kawano et al.
patent: 6124733 (2000-09-01), Sharpe-Geisler
Mills & Onello LLP
Nguyen Long
LandOfFree
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