Static information storage and retrieval – Addressing – Sync/clocking
Patent
1996-12-16
1998-08-18
Zarabian, A.
Static information storage and retrieval
Addressing
Sync/clocking
326 93, G11C 800
Patent
active
057966745
ABSTRACT:
A set of series-connected N-MOSFETs 1, 3 and a set of series-connected N-MOSFETs 2, 4 are connected in parallel with each other between a pull-up node e1 of a P-MOSFET 5 and a GND. A set of series-connected P-MOSFETs 11, 13 and a set of series-connected P-MOSFETs 12, 14 are connected in parallel with each other between a power source VDD and a pull-down node f1 of an N-MOSFET 15. The pull-down node f1 is connected to the gate of an N-MOSFET 16, and the pull-up node e1 is connected to the input gate of an inverter 17. The transition of the signal inputted to each transistor is detected thereby to generate a pulse signal at the output OUT of the inverter. Gate signal b1 is delayed behind gate signal a1 by an amount of one inverter stage, gate signal c1 is delayed behind gate signal a1 by an amount of three inverter stages, and gate signal d1 is delayed behind gate signal b1 by an amount of three inverter stages. A signal with a sufficient pulse width can thus be generated against a thin input pulse without extending the pulse width or shaping of waveform in the preceding stage.
REFERENCES:
patent: 5159574 (1992-10-01), Kim
patent: 5198709 (1993-03-01), O'Connell
patent: 5306963 (1994-04-01), Leak
patent: 5587673 (1996-12-01), MacDonald
Sharp Kabushiki Kaisha
Zarabian A.
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