Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2000-08-08
2004-09-28
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S057000, C702S079000, C702S187000
Reexamination Certificate
active
06799127
ABSTRACT:
FIELD OF THE INVENTION
In general, the present invention relates to the field of digital analysis and bus data generated from a device under test. More specifically, the present invention relates to accurately positioning a logic analyzer sample within the data valid window of a device under test.
BACKGROUND OF THE INVENTION
As known by those skilled in the art, a logic analyzer is an electronic instrument used to detect, analyze, and display digital voltage signals. Because of the increasing operational complexity of target devices, logic analyzers provide many configuration functions. In addition, as target devices continue to operate at faster speeds and with more complexities, simpler methods of interacting with the logic analyzer's user interface are needed.
Conventional logic analyzers include a graphical user interface that allows the user to select and configure a variety of features and functions built into the instrument. The graphical user interface is generally made available on a display integrated with the logic analyzer, and may additionally be made available on a remote terminal that communicates with the logic analyzer. A logic analyzer generally allows data sampling in a synchronous clock mode (i.e. state mode) or an asynchronous clock mode (i.e. timing mode). In a state mode measurement, the logic analyzer is clocked by a signal from the device under test. Each time the device under test's dock signal becomes valid, the analyzer samples the data. Since the analyzer's sampling is controlled by the device under test's clock, state mode measurements are said to be synchronous to the device under test. In a timing mode measurement, the logic analyzer is clocked according to its own internal clock signal. Since this clocking signal is not related to the clock from the device under test, timing mode measurements are said to be asynchronous to the device under test.
As with any synchronous digital circuit, a logic analyzer operating in a synchronous sampling mode (i.e. state mode) latches data appearing at its inputs on each active clock transition supplied by the device under test. Because of this, the analyzer requires the input logic signals to be stable for a period of time before the clock transition (setup time) and after the clock transition (hold time) so that it can accurately capture the desired data. This combination of setup and hold times is known as the analyzer's setup/hold window. The device under test is also has a setup/hold window that defines the length of time data will be valid on a bus. This is known as the data valid window. A critical relationship exists between the device under test's data valid window and the logic analyzer's setup/hold window. In order for the logic analyzer to capture valid data, its setup/hold window must be positioned within the device under test's data valid window as shown in FIG.
1
.
FIG. 1
shows a clock signal
100
and a representation of bus data
110
. The data valid window
120
is shown relative to a clock signal transition
130
. The logic analyzer's setup/hold window
140
must fit within the data valid window
120
.
Because the position of the data valid window relative to the clock varies for different types of buses, logic analyzers must provide an adjustable setup/hold window so that the sample position can be optimized. As systems become faster, margins for error are becoming smaller. Setup precision is becoming more important.
Logic analyzers generally provide a simple user interface for adjusting the setup and hold values.
FIG. 2
shows the setup/hold settings graphical user interface
200
from a prior art logic analyzer. This graphical user interface allows the user to adjust the setup/hold values
210
on each individual channel from 2.5 ns setup/0.0 ns hold to 0.0 ns setup/2.5 ns hold in 100 ps increments. This gives the user the control over the analyzer's sample position in the fine resolution needed to optimize the analyzer's sampling performance. While the user is presented with all of the functionality necessary for optimizing the logic analyzer's sample position, the prior art also presents the end user with numerous disadvantages and obstacles for defining the optimal setup/hold values quickly and accurately.
First, the end-user is provided no information concerning where the device under test's stable and transitioning data regions are relative to the dock edge. The user does not have any indication about how much the setup/hold window might need to be adjusted or in what direction.
Second, the user interface provides no visual feedback concerning the location of the setup/hold window relative to the data valid window. This leads to a lengthy and error prone trial and error approach to defining the necessary values.
A third disadvantage of the prior art is that the user interface uses standard default values for the setup/hold settings that have no relationship to the end user's device under test and are therefore a simple guess that may or may not work for the users measurements.
A fourth disadvantage is that while the user's real end goal is to correctly place the logic analyzer's sampling position in reference to the device under test's clock signal, the information is presented in terms of setup/hold values rather than sample position. Accordingly, the user must form a mental model of how these two concepts relate to on another.
Finally, the user can only see the setup/hold values for a single bus or single signal at any given time. In addition, the user cannot easily switch between setting values for individual signals or complete buses. If the user switches to the “All Bits” setting
220
(i.e. setting values for the bus as a whole) as shown in
FIG. 2
, all of the individual settings that may have been set will be lost.
Accordingly, there is a need for a logic analyzer graphical user interface with a visual display of where the actual stable and transitioning regions on each of the system's signals are in reference to the device under test's clock transition. There is also a need for displaying the logic analyzer settings in terms of sample position rather than setup/hold so that the user can more easily relate the information to their end goal. There is a further need to display the sample position visually relative to the clock edge and the stable and transitioning data regions. Finally, there is a need to display a suggested sample position as a default value that is relative to the device under test rather than a preset default sample position that is the same regardless of the device under test.
REFERENCES:
patent: 6054984 (2000-04-01), Alexander
patent: 6246408 (2001-06-01), Alexander
patent: 6396517 (2002-05-01), Beck et al.
patent: 6463392 (2002-10-01), Nygaard et al.
patent: 6556223 (2003-04-01), Tran et al.
Nygaard, Jr. Richard A
Shay Jennifer
Sontag David N
Agilent Technologie,s Inc.
Hoff Marc S.
Suarez Felix
Trumper Regan L.
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