Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-02-03
2001-10-30
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S374000, C326S027000, C326S087000, C307S412000
Reexamination Certificate
active
06310496
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a bus driver and, more particularly, to a signal transition accelerating driving circuit and a bus driving system implemented by the signal transition accelerating driving circuits.
DESCRIPTION OF THE RELATED ART
The signal transition accelerating bus driver aims at elimination of a time lug from a signal propagation along a signal line with a large time constant. Typical examples of the signal transition accelerator are disclosed in Japanese Patent Publication of Unexamined Application No. 8-186482 and in “Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnection Signals of Sub-quarter Micron VLSI”, 1995 Symposium on VLSI Circuits Digest of Technical Papers. The prior art signal transition accelerators detect a signal transition propagated along a bus line, and accelerate the signal transition for eliminating a time lug due to the gentle transition.
Another prior art bus driver system is disclosed in Japanese Patent Publication of Unexamined Application No. 9-50693, and is incorporated in a memory device. The prior art bus driver system uses a non-selected bus driver in order to assist a signal transition on a bus line, thereby accelerating a signal propagation to the output end of the bus line without increase in the current driving capability of the plural bus drivers.
FIG. 1
illustrates a typical example of the signal transition accelerating bus driver. The prior art signal transition accelerating bus driver is broken down into an output driver
1
, a gate circuit
2
and a signal transition accelerator
3
. A p-channel enhancement type field effect transistor Qp
1
and an n-channel enhancement type field effect transistor Qn
1
are connected in series between a high level line
4
and a low level line
5
, and the series combination of the p-channel enhancement type field effect transistor Qp
1
and the n-channel enhancement type field effect transistor Qn
1
serves as the output driver
1
. The p-channel enhancement type field effect transistor Qp
1
and the n-channel enhancement type field effect transistor Qn
1
complementarily turn on and off, and supply the high level or the low level to a bus line
6
.
The gate circuit
2
includes two transfer gates
7
/
8
and an inverter
9
. The transfer gates
7
and
8
are connected between a data line
10
and the gate electrodes of the field effect transistors Qp
1
/Qn
1
. An enable signal line
11
is connected to the inverter
9
and the first control nodes of the transfer gates
7
/
8
, and the inverter
9
is connected to the second control nodes of the transfer gates
7
/
8
. The enable signal line
11
propagates the enable signal EBL
1
to the first control nodes of the transfer gates
7
/
8
, and the inverter
9
supplies the inverted signal CEBL
1
of the enable signal EBL
1
to the second control nodes of the transfer gates
7
/
8
. When the enable signal EBL
1
is in the high level, the transfer gates
7
/
8
turn on, and a data signal Sin is transferred through the transfer gates
7
/
8
to the gate electrodes of the field effect transistors Qp
1
/Qn
1
.
The signal transition accelerator
3
includes a NAND gate
12
, a NOR gate
13
, delay circuits
14
/
15
and transfer gates
16
/
17
. The NAND gate
12
has two input nodes one of which is directly connected to the bus line
6
and the other of which is connected through the delay circuit
14
to the bus line
6
. Similarly, the NOR gate
13
has two input nodes one of which is directly connected to the bus line
6
and the other of which is connected through the delay circuit
15
to the bus line
6
. The output node of the NAND gate
12
is connected through the transfer gate
16
to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
, and the output node of the NOR gate
13
is connected through the transfer gate
17
to the gate electrode of the n-channel enhancement type field effect transistor Qn
1
. Each of the delay circuits
14
/
15
is implemented by an odd number of inverters connected in series, and both delay circuits
14
/
15
introduce a predetermined delay time into the propagation of a potential level on the bus line
6
. The potential level on the bus line
6
is propagated to the other end of the bus line
6
as a data signal Sout, and returns to the signal transition accelerator as a bus status signal BS
1
. The delay circuits
14
/
15
supply an inverted signal CBS
1
to the other input node of the NAND gate
12
and the other input node of the NOR gate
13
. The NAND gate
12
and the NOR gate
13
offer a feedback loop to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
or the gate electrode of the n-channel enhancement type field effect transistor Qn
1
depending upon the bus status signal BS
1
. The inverter
9
supplies the inverted signal CEBL
1
to the first control nodes of the transfer gates
16
/
17
, and the enable signal line
11
supplies the enable signal EBL
1
to the second control nodes of the transfer gates
16
/
17
. When the enable signal EBL
1
is in the low level, the transfer gates
16
/
17
turn on, and the NAND gate
12
and the NOR gate
13
are connected through the transfer gate
16
to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
and through the transfer gate
17
to the gate electrode of the n-channel enhancement type field effect transistor Qn
1
.
The prior art signal transition accelerating bus driver drives the bus line
6
in response to the data signal Sin or the potential level on the bus line
6
. Description is firstly made on the driving operation on the bus line
6
in response to the data signal Sin. The data signal Sin and the data signal Sout are assumed to be in the high level and in the low level, respectively. Accordingly, the bus status signal BS
1
and the inverted signal CBS
1
are in the low level and in the high level, respectively.
The enable signal EBL
1
is firstly changed to the high level. The enable signal EBL
1
causes the transfer gates
7
/
8
and the transfer gates
16
/
17
to turn on and off, respectively. The data signal Sin is changed from the high level to the low level, and the potential change is transferred to the gate electrode of the p-channel enhancement type field effect transistor Qp
1
and the gate electrode of the n-channel enhancement type field effect transistor Qn
1
. The data signal Sin gives rise to decrease the potential level at the gate electrode of the p-channel enhancement type field effect transistor Qp
1
and the gate electrode of the n-channel enhancement type field effect transistor Qn
1
. The p-channel enhancement type field effect transistor Qp
1
is varied toward the on-state, and the n-channel enhancement type field effect transistor Qn
1
is varied toward the off-state. The p-channel enhancement type field effect transistor Qp
1
starts to flow electric current from the high level line
4
to the bus line
6
. The electric current raises the potential level on the bus line
6
, and the output signal Sout is changed from the low level to the high level.
On the other hand, if the enable signal EBL
1
is changed to the low level, the prior art signal transition accelerating bus driver becomes responsive to the potential level on the bus line
6
. The enable signal EBL
1
causes the transfer gates
7
/
8
and the transfer gates
16
/
17
to turn off and on, respectively. As a result, the gate electrode of the p-channel enhancement type field effect transistor Qp
1
and the gate electrode of the n-channel enhancement type field effect transistor Qn
1
are electrically isolated from the data line
10
.
The potential level on the bus line
6
is assumed to rise toward the high level. The delay circuits
14
/
15
keep the inverted signals CBS
1
in the high level. When the potential level on the bus line
6
exceeds the threshold of the NAND/NOR gates
12
/
13
, the bus status signal BS
1
enables the NAND gate
12
, and disables the NOR gate
13
. The NOR gate
13
sup
Callahan Timothy P.
Foley & Lardner
NEC Corporation
Nguyen Minh
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