Signal transfer circuit for synchronous memory device

Details Signal transfer circuit for synchronous memory device Signal transfer circuit for synchronous memory device

1996-05-01

1997-05-06

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36523002, G11C 1300

Patent

active

056277946

ABSTRACT:
A signal transfer circuit for a synchronous memory device, comprising an input terminal for inputting a clock signal, an internal address generator for generating an internal address signal, a multiplexing circuit for selectively transferring an external address signal and the internal address signal from the internal address generator, a multiplexing controller for controlling the operation of the multiplexing circuit in response to the clock signal from the input terminal, an internal circuit for generating a data signal in response to the external or internal address signal transferred by the multiplexing circuit, a data output buffer for buffering the data signal generated by the internal circuit and outputting the buffered data signal externally, an output buffer controller for controlling the operation of the data output buffer in response to the clock signal from the input terminal, a switching circuit connected between the internal circuit and the data output buffer, for performing a switching operation to transfer the data signal from the internal circuit to the data output buffer, and a switching controller for controlling the operation of the switching circuit in response to the clock signal from the input terminal.

REFERENCES:
patent: 5287320 (1994-02-01), Adachi
patent: 5424982 (1995-06-01), Kato
patent: 5495452 (1996-02-01), Cha

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