Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1998-11-06
2002-05-21
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C375S365000, C370S509000, C370S514000
Reexamination Certificate
active
06393082
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal synchronism detecting circuit, and more specifically to a signal synchronism detecting circuit having a serial-to-parallel conversion function of converting an inputted serial data in accordance with a predetermined signal.
2. Description of Related Art
In the prior art, there has been known a signal synchronism detecting circuit for detecting a word synchronism (frame synchronism, byte synchronism) discriminating the boundary or delimiter of bit groups in a time sequence in order to identify the roles of respective bits. In a high speed serial transmission field of a communication system, some of the signal synchronism detecting circuit has a function of receiving a high speed serial data coded by a
8
B
10
B encoder and of executing a serial-to-parallel conversion. The high speed serial data includes a comma signal, which is a delimiter bit group for delimiting data bit groups (each formed of a predetermined number of continuing bits) from each other. The comma signal includes two kinds, namely, “1100000101” and its inversion “0011111010”. The comma signal is used only at a heading of the word (frame, byte). A receiving side can properly perform the serial-to-parallel conversion by taking the word synchronism on the basis of the comma signal.
Here, a proper serial-to-parallel conversion is that when a received serial signal is serial-to-parallel-converted to restore a parallel signal before the sending, a heading bit of the serial data is correctly recognized, and the parallel signal is restored with no deviation in bit position.
Referring to
FIGS. 8A
to
8
G, a general method for taking the word synchronism in the serial data is diagrammatically illustrated.
Here, consider that as shown in
FIG. 8A
, for example, two 4-bit parallel signals A
1
to A
4
and B
1
and B
4
of 1 Gbps are parallel-to-serial-converted to 4:1 at a sending side, and a serial data of 4 Gbps is received at a receiving side. When the serial data of 4 Gbps is serial-to-parallel-converted to 1:2 to generate two serial data trains, since the serial data of 4 Gbps is continuously received, if the data conversion of 1:2 is performed without taking the word synchronism, two data patterns shown in
FIGS. 8B and 8C
are obtained. Alternatively, when the serial data of 4 Gbps shown in
FIG. 8A
is serial-to-parallel-converted to 1:4, since the serial data of 4 Gbps is continuously received, if the data conversion of 1:4 is performed without taking the word synchronism, four data patterns shown in
FIGS. 8D
,
8
E,
8
F and
8
G are obtained.
For example, if the word synchronism is conducted when the serial data of 4 Gbps shown in
FIG. 8A
is obtained, when the serial data is converted to the two serial data trains, the serial data is properly converted to the data pattern shown in FIG.
8
B. In addition, when the serial data is converted to the four serial data trains, the serial data is properly converted to the data pattern shown in FIG.
8
D. If the word synchronism is conducted when the serial data is converted to the two serial data trains of 2 Gbps, it is necessary to detect in which of the two conditions shown in
FIGS. 8B and 8C
the two serial data trains are. In addition, if the word synchronism is conducted when the serial data is converted to the four serial data trains of 1 Gbps, it is necessary to detect in which of the four conditions shown in
FIGS. 8D
to
8
G the four serial data trains are.
Here, the case of taking the word synchronism for the serial data coded by the
8
B
10
B encoder mentioned above will be described. In a fiber channel or the like, at a sender side, after the serial data is coded by the
8
B
10
B encoder, the data is transmitted. At a receiving side, the word synchronism is taken in order to properly perform the serial-to-parallel conversion on the basis of the received serial data. In the serial data coded by the
8
B
10
B encoding, the number of the same continuing bits (namely, continuing 0s or continuing 1s) is limited to 4 bits at maximum. Only one existing 5-bit signal formed of the same bits is 5 continuing 0s or 1s included in the comma signal.
FIGS. 9A
to
9
F diagrammatically illustrate how the word synchronism is taken on the basis of the comma signal. When two kinds of comma signal shown in of
FIGS. 9A and 9B
are received as the serial data of 4 Gbps, if the word synchronism is taken in the condition of 4 Gbps, it is sufficient if the above mentioned two kinds of bit group are detected. However, if the serial data is converted to two serial data trains without taking the word synchronism in the condition of 4 Gbps, the comma signal assumes four different patterns constituted by the two converted serial data trains of 2 Gbps, as shown in
FIGS. 9C
,
9
D,
9
E and
9
F. Namely, if the word synchronism is taken in the condition of 2 Gbps, it is necessary to detect the word synchronism from the four different converted serial data train patterns.
Referring to
FIG. 10
, there is shown a circuit diagram of a prior art signal synchronism detecting circuit for the 4 Gbps serial data. The shown signal synchronism detecting circuit includes a 1/10 frequency dividing counter
21
receiving a clock signal of 4 Gbps, a serial-to-parallel converter section
22
and a data input section
23
formed of flipflops F/F-
0
to F/F-
9
. In the word synchronous circuit having this construction, if the 4 Gbps serial data is inputted to the data input section
23
, the word synchronism is taken by using the clock signal of 4 Gbps, and the serial-to-parallel conversion of 1:10 is performed to output a 10-bit parallel signal of 400 Mbps. Incidentally, “A” and “B” in
FIG. 10
indicate the comma signal.
Referring to
FIG. 11
, there is shown a circuit diagram of a prior art signal synchronism detecting circuit for the 2 Gbps serial data. The shown signal synchronism detecting circuit includes a data input section
24
, a 1/5 frequency dividing counter
26
, and a serial-to-parallel converter section
27
. The data input section
24
includes a converter section
25
for conducting a 1:2 data conversion for the received 4 Gbps serial data, so as to generate two serial data trains of 2 Gbps. In the word synchronous circuit having this construction, after the received 4 Gbps serial data is converted to the two serial data trains of 2 Gbps, the word synchronism is taken, and the serial-to-parallel conversion of 2:10 is performed to output a 10-bit parallel signal of 400 Mbps.
As mentioned above, if the signal synchronism such as the word synchronism is taken in the condition having a high bit rate, the number of patterns to be detected is small, and therefore, the circuit scale is small and the power consumption is low. In addition, since the clock frequency for operating the circuit to detect the signal synchronism is high, the data transfer delay occurring in the signal synchronism is small, and the latency of the overall system is small. However, since the synchronism is detected at the high bit rate, high speed operating circuits and devices become necessary. In addition, since it is necessary to distribute the high speed clock, there is possibility that a clock skew occurs between various circuit blocks. Therefore, there is a troublesome in cautiously distributing the high speed clock.
On the other hand, in the case that the signal synchronism is taken after the data conversion is conducted to lower the bit rate, the high speed operating circuits and devices become unnecessary, and correspondingly, since it also becomes unnecessary to distribute the high speed clock, there is no possibility of a clock skew. However, if the signal synchronism is taken after the bit rate is lowered, the number of patterns to be detected increases, and the scale of the circuit required for the synchronism detection correspondingly becomes large. Furthermore, since the clock frequency for operating the circuit to detect the signal synchronism is low, the data transfer delay occurring in the word synchro
Bocure Tesfaldet
McGinn & Gibb PLLC
NEC Corporation
Phu Phuong
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