Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-07-27
2003-09-30
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S118000, C341S120000, C341S144000, C341S155000, C341S156000
Reexamination Certificate
active
06628217
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing second order delta sigma modulators generally and, more particularly, to a method and/or architecture for efficient and accurate scaling of input and reference signals to avoid saturation in modulator integrators.
BACKGROUND OF THE INVENTION
Conventional delta sigma analog-to-digital converters consist of a modulator followed by a digital filter. The purpose of the modulator is to digitize an analog input signal and shape the noise spectrum such that the quantization noise is forced to high frequencies. The digital filter (typically a low pass digital filter) then removes the high frequency noise to provide an improved signal-to-noise ratio (SNR). The modulator can be first, second, third, etc. order depending on a number of integrators. Higher order modulators force more of the noise to higher frequencies for a given oversampling rate. Therefore, a better SNR is achieved with higher order modulators. However, higher order modulators have increased stability problems and are difficult to design.
Referring to
FIG. 1
, a conventional second order delta sigma modulator
10
is shown. The modulator
10
consists of two fully differential integrators
12
and
14
followed by a latching comparator
16
and a flip flop
18
. The outputs of the flip flop
18
M_OUT and M_OUT_b drive switches that generate the reference voltages VREF
1
and VREF
2
which are essentially the DAC output voltages. The modulator
10
generates a 1 bit data stream. Therefore, the modulator
10
uses a 1 bit DAC to guarantee ideal differential nonlinearity (DNL). Higher bit DACs can also be used to achieve higher throughput rates at the expense of higher potential DNL.
Two different reference voltage levels can be used with the modulator
10
, an external reference level EXT_REF_P (equal to VCC) and an internal reference level. INT_REF (equal to twice the on chip bandgap voltage). The internal reference level INT REF is used when an absolute reference level is required (e.g., in monitoring a battery voltage), The external reference level EXT_REF_P enables ratiometric operation with a level equal to VCC. The reference negative level in each mode is REF_N and typically equals OV. Depending on the outputs M_OUT and M_OUT_b, the levels VREF
1
and VREF
2
will be at the positive or negative reference levels (for a given mode) which ensures negative feedback such that the integrators
12
and
14
do not saturate.
Typically, gain levels of the integrators
12
and
14
should be less than 1 and the input signal ANALOG_IN must be attenuated to ensure no degradation in SNR over the input range. An input gain factor of 0.5 and integrator gain factors of 0.25 together with a bandgap gain of 2 provide a reasonable input range for an internal reference mode.
When the switches P
1
are active, the first integrator
12
is auto zeroed and the analog inputs ANALOG_IN are being sampled together with VREF
1
on the upper side and VREF
2
on the lower side. The autozero switch P
1
is opened first while the switches P
1
_DEL connected to the analog inputs ANALOG_IN and the VREF
1
and VREF
2
signals, respectively, are opened a short delay after. The integrator
12
avoids a signal dependent charge injection error, since the input nodes ANALOG IN are presented to an operational amplifier
20
and have high impedance during the delay interval. Additionally, the switches P
1
, P
1
_DEL, and P
2
and P
2
_DEL may be driven by non-overlapping clocks. Next, the switches P
2
and P
2
_DEL turn on. The left hand sides of the input capacitors C are then connected to AGND which is typically half the effective reference range. Since the feedback capacitors equal
4
C, the integrator
12
has a gain of ¼.
The voltages VREF
1
and VREF
2
are multiplied by ¼while the input ANALOG_IN is multiplied by {fraction (1/2*1/4)}or ⅛. The switching arrangement of the switches and the integration switches P
1
, P
1
_DEL, P
2
and P
2
_DEL is such that VREF
1
has the opposite polarity of ANALOG_IN_P, (i.e., there is negative feedback). The location of the feedback switches P
2
_DEL in series with the feedback capacitors
4
C causes charge injection error, since the outputs of the integrator
12
will have different voltage levels.
The modulator
10
has one or more of the following disadvantages:
the input signal ANALOG_IN needs to be attenuated with respect to the reference level;
the bandgap voltage needs to be gained appropriately to have a reasonable input range; and/or
charge injection error due to the location of the feedback switch in series with the integrator feedback capacitors.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a reference generation circuit and a modulator. The reference generation circuit may be configured to generate a first one or more reference voltages and a second one or more reference voltages. The modulator may be configured to present an output signal in response to an input signal, the first reference voltages and the second reference voltages. A gain between the output signal and the input signal may be set by a capacitor ratio in said modulator.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a second order delta sigma modulator that may (i) set a gain by selecting capacitor ratios, (ii) provide well controlled gains, (iii) provide lower power dissipation, (iv) not need additional active circuitry (e.g., operational amplifiers) and accurate resistors, (v) be implemented in standard CMOS process and/or (vi) lower charge injection error due to placement of feedback switches.
REFERENCES:
patent: 5057839 (1991-10-01), Koch
patent: 5691720 (1997-11-01), Wang et al.
patent: 5874912 (1999-02-01), Hasegawa
patent: 5995035 (1999-11-01), Signell et al.
patent: 6097326 (2000-08-01), Opris et al.
patent: 6147522 (2000-11-01), Rhode et al.
patent: 6255974 (2001-07-01), Morizio et al.
“The Design of Sigma-Delta Modulation Analog-to-Digital Converters”, By Bernhard E. Boser and Bruce A. Wooley, IEEE Journal of Solid-State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1298-1308.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nguyen Linh Van
Tokar Michael
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