Signal sampling device for minimizing the errors effecting succe

Details Signal sampling device for minimizing the errors effecting succe Signal sampling device for minimizing the errors effecting succe

1988-12-02

1991-01-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307529, 307353, H03K 500, H03K 5159, G06G 716, G06G 700

Patent

active

049839250

ABSTRACT:
An improved device for sampling signals to minimize the errors introduced in the stored samples includes first and second sampling elements whose respective sampling and holding periods are offset with respect to each other, an amplifier applying a gain G to the difference between the input voltage and the sample stored by the first element, before transmitting it to the second element, and a summing circuit for adding to the samples stored by the first element a fraction of the samples stored by the other element. The sampling errors are reduced by a factor G equal to the gain value.

REFERENCES:
patent: 3641563 (1972-02-01), Cushman et al.
patent: 4004239 (1977-01-01), Clarke
patent: 4352070 (1982-09-01), Beauducel et al.
patent: 4691125 (1987-09-01), Rybichi
George Erdi, "A Precision FET-Less Samle-and -Hold with High Charge-to-Droop Current Ratio", IEEE Journal of Solid-State Circuits, vol. SC-13, No. 16, Dec. 1978, pp. 864-873.
French Search Report, FR 8716848.

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