Signal sampling circuit with redundancy

Details Signal sampling circuit with redundancy Signal sampling circuit with redundancy

1993-01-19

1996-09-17

Nguyen, Hoa T.

Excavating

G11C 2900

Patent

active

055576184

ABSTRACT:
A circuit modifies a fast-in, slow-out data acquisition system to provide a redundant analog data acquisition cell (aR) that can be substituted for a defective cell without adversely affecting the timing between acquired samples. This circuit includes a plurality of signal acquisition cells (a1-an) including at least one redundant cell arranged in a row, a source of sample and hold clock signals (b1-bn) for the signal acquisition cells, and a corresponding row of demultiplexers (D1-Dn). Each acquisition cell has an analog signal input and a sample and hold clock signal input that determines when the analog signal is to be sampled. The demultiplexers each have a signal input, a select input, and at least two outputs, with the input being coupled to one of the sample and hold clock signals, and the outputs being coupled to the sample and hold clock inputs of two adjacent signal acquisition cells. The select inputs of the demultiplexers are controlled by either a shift register (FF1-FFn), burnable fuse links (f1-fn), or some other method, to select which demultiplexer output is to receive the sample and hold signal clock so that when a defect is found in one of the signal acquisition cells or related circuitry, the sample and hold clock signal for the defective signal acquisition cell are routed to a different signal acquisition cell. Dummy demultiplexers (DD1-DDn) provide equivalent stray capacitance and other transmission path characteristics to all sample and hold clock signal paths.

REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4723227 (1988-02-01), Murotani
patent: 5200983 (1993-04-01), Kogan
patent: 5255234 (1993-10-01), Seok
patent: 5274593 (1993-12-01), Proebsting
patent: 5297085 (1994-03-01), Choi et al.
patent: 5315551 (1994-05-01), Hirayama

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