Coded data generation or conversion – Sample and hold
Reexamination Certificate
2008-09-12
2011-10-11
Jeanglaude, Jean (Department: 2819)
Coded data generation or conversion
Sample and hold
C341S155000
Reexamination Certificate
active
08035539
ABSTRACT:
A sampling circuit includes multiple sampling channels adapted to sample the signal in time-multiplexed fashion. Each sampling channel includes a respective track-and-hold circuit connected to a respective analogue to digital converter via a respective output switch. The output switch of each channel opens for a tracking time period when the track-and-hold circuit is in a tracking mode for sampling the signal, and closes for a holding time period when the track-and-hold circuit is in a holding mode for outputting the sampled signal. In an embodiment, the holding time period includes a settling time period that is at least as long as the tracking time period. The settling time period is used by the track-and-hold circuit to charge an input capacitance of the analogue to digital converter to a voltage according to the sampled signal.
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Louwsma, S. M., et al; “A 1.6 GS/s, 16 Times Interleaved Track & Hold With 7.6 ENOB in 0.12/spl mu/m CMOS (ADC Application)”; Solid-State Circuits Conference ESSCIRC 2004; IEEE Piscataway, NJ, US; Sep. 2004; 4 Pages.
Louwsma Simon Minze
Vertregt Maarten
Jeanglaude Jean
NXP B.V.
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