Pulse or digital communications – Miscellaneous
Reexamination Certificate
2007-01-23
2007-01-23
Ha, Dac V. (Department: 2611)
Pulse or digital communications
Miscellaneous
C375S354000
Reexamination Certificate
active
10152804
ABSTRACT:
This invention provides a signal transfer technique capable of realizing stable high rate data transfer and the reduction of a layout area. A system (semiconductor device) for realizing a high rate data transfer circuit method includes: a transmission circuit which consists of a normal signal transmitter and a receiving amplifier starting signal transmitter; a receiving circuit which consists of a receiving amplifier and a receiving amplifier starting signal receiver; a normal signal line and a receiving amplifier starting signal line connected between the transmission circuit and the receiving circuit; and the like. The normal signal transmitter includes a circuit which changes an output level for a specific period in accordance with the level of a normal signal and a circuit which controls the normal signal line to allow the normal signal line to function between VDD and VSS. The receiving amplifier includes a capacitance and a circuit which fetches a voltage of the capacitance at predetermined change timing of a control signal and then outputs a signal based on the fetched voltage of the capacitance. The receiving amplifier consists of a chopper comparator, and the normal signal line consists of a single transmission path.
REFERENCES:
patent: 4766567 (1988-08-01), Kato
patent: 6392450 (2002-05-01), Yoshida et al.
patent: 6594769 (2003-07-01), Dabral et al.
patent: 6-37854 (1992-07-01), None
patent: 6-37857 (1992-07-01), None
patent: 6-78003 (1992-08-01), None
patent: 7-44473 (1993-07-01), None
patent: 7-46135 (1993-08-01), None
patent: 7-95249 (1993-09-01), None
patent: 9-321810 (1996-05-01), None
patent: 10-303994 (1997-04-01), None
patent: 10-327202 (1997-07-01), None
patent: 2000-49575 (1998-07-01), None
patent: 2000-244586 (1999-03-01), None
Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyosi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawaski, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Zenya Kawaguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, “A 0.18μm 256Mb DDR-SDRAM with Low-Cost Post Mold-Tuning Method for DLL Replica”, ISSCC 2000/Sssion 24/DRAM/Paper WP 24.6.
Hideo Mukai, Takeshi Nagai, Satoru Takase, Seiro Imai, Hiroshi Maejima, Mikihiko Ito, Teshiteru Yamamoto, Hiroko Waki, Kiyofumi Sakurai, Takaniko Hara, Masaru Koyanagi, Kaoru Nakagawa, “New Architecture for Cost-Efficient High-Performance Multiple-Bank RDRAM”, 2000 IEEE International Solid State Circuits Conference, pp. 400-401.
A. Marquez, Esq. Juan Carlos
Elpida Memory Inc.
Fisher Esq. Stanley P.
Ha Dac V.
Reed Smith LLP
LandOfFree
Signal receiving circuit, semiconductor device and system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal receiving circuit, semiconductor device and system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal receiving circuit, semiconductor device and system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3811084