Signal processor having multiple paralleled data acquisition cha

Multiplex communications – Wide area network – Packet switching

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34082508, 367 23, 370 941, G08C 1508

Patent

active

054576881

ABSTRACT:
A system for acquiring data from a plurality of analog signal sources inces a multiple-channel asynchronously operating first-stage subsystem each channel of which outputs composite digital representations of the analog signal, which in turn are passed to a digital processor in which the data are used by a second-stage subsystem (40). The second-stage subsystem (40) has a plurality of signal processing units (48), each having an input coupled to a different output channel of the first-stage subsystem. Each of the signal processing units includes a first buffer (48-2). The system also includes a plurality of data processing units (52, 54). The data processing units have an input coupled to an output of a first buffer of the signal processing units. Each of the data processing units operates under an operating program providing formatting into a data packet having a predetermined format. An arbitration and transmission unit (44) has an input coupled to the data processing units and sequentially polls then so as to receive a data packet from a data processing unit having a data packet available. The transmission unit buffers prior to a transmission of the data packet. Each of the signal processing units generates a status signal in response to the associated first buffer reaching a predetermined partially full condition. The transmission unit is responsive to the generation of status signals for interrupting the sequential polling. As a result, a possibility of data overruns and a loss of transducer data is substantially eliminated.

REFERENCES:
patent: 4796025 (1989-01-01), Farley et al.
patent: 5101199 (1992-03-01), Suzuki
patent: 5237322 (1993-08-01), Heberle

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