Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1999-03-23
2003-07-29
Phu, Phuong (Department: 2631)
Pulse or digital communications
Equalizers
Automatic
C708S323000
Reexamination Certificate
active
06600779
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal processor for processing a read signal, and, more particularly, to improvements on feedback loop control for decision feedback equalizers, which are used in a read channel IC for a hard disk device and fast data communication devices, and in circuits for correcting errors in read data.
A read channel IC in a hard disk device receives an analog signal, read from a hard disk by a read head. A waveform equalizer in the read channel IC converts the analog signal to a digital signal. The read channel IC decodes the digital signal and converts the decoded digital signal to a parallel signal.
There are two types of waveform equalizers: a PRML (Partial Response and Maximum-Likelihood decoding) type waveform equalizer and a decision feedback equalizer (DFE). The PRML type waveform equalizer needs a high-precision digital filter and equalizer filter, which stands in the way of increasing processing speed and circuit miniaturization. The DFE has a relatively simple circuit structure, which makes it a good candidate for improving the speed of reading out recorded data and reducing the size of the equalizer.
FIG. 1
is a schematic block diagram of a first conventional decision feedback equalizer (DFE)
11
. The DFE
11
has a prefilter (feed-forward filter)
12
, an adder
13
, a decision unit
14
, a shift register
15
, and a feedback filter
16
. The prefilter
12
supplies a filtered analog signal to the adder
13
. The adder
13
adds the filtered analog signal and the output signal of the feedback filter
16
, and sends the added output to the decision unit
14
. The decision unit
14
compares the output voltage of the adder
13
with a predetermined reference voltage, and sends a decision signal S
1
of “1” or “0” to the shift register
15
. That is, the decision unit
14
converts the output signal of the adder
13
to a digital signal.
The shift register
15
includes registers
15
a
whose quantity corresponds to the number of the taps of the feedback filter
16
(eight in this example). The individual registers
15
a
store the decision signal S
1
from the decision unit
14
one after another in synchronism with a clock signal CLK. Accordingly, sampled, old data is stored in the shift register
15
.
The feedback filter
16
, which is preferably an FIR (Finite Impulse Response) filter, includes multipliers
17
corresponding in number to the taps, an adder
18
, and a digital-analog converter (DAC)
19
. The multipliers
17
receive 8-bit data from the shift register
15
and perform multiplication on the 8-bit data using predetermined filter coefficients &ohgr;7 to &ohgr;0. The adder
18
adds the operational results from the multipliers
17
. The DAC
19
converts the added result from the adder
18
to an analog signal and supplies the analog signal to the adder
13
. In this manner, the feedback filter
16
computes the feedback response (the analog amount of the signal to be supplied to the adder
13
(feedback amount)) using the data stored in the shift register
15
. The feedback loop, which is formed by the adder
13
, the decision unit
14
, the shift register
15
and the feedback filter
16
, eliminates interference between codes (symbols) included in a digital signal. The digital signal (reproduced signal) which is then free of code interference is output from one register
15
a
in the shift register
15
.
The time the multipliers
17
and the adder
18
in the DFE
11
needs to compute the feedback response restricts the speed of the reading operation. In other words, the speed of the DFE
11
is limited by the speed of the multipliers
17
and the adder
18
.
FIG. 2
is a schematic block diagram of a second conventional decision feedback equalizer (DFE)
21
. In
FIG. 2
, the same reference numerals as given to the elements of the DFE
11
in
FIG. 1
are used for corresponding elements. The DFE
21
comprises a prefilter
12
, an adder
13
, a decision unit
14
, a shift register
15
and a feedback filter
22
. The feedback filter
22
includes an address decoder
23
, a memory (RAM)
24
and a DAC
25
. The DFE
21
which uses the RAM
24
is called RAM-DFE.
The RAM
24
has a plurality of areas
24
a
for storing feedback response data, which is generated by using 8-bit pattern data output from the shift register
15
. The feedback response data is acquired by performing an operation on the 8-bit pattern data using predetermined filter coefficients &ohgr;7 to &ohgr;0.
The decoder
23
receives the 8-bit pattern data from the shift register
15
and supplies the RAM
24
with an address signal for selecting the area
24
a
where the feedback response data corresponding to the received pattern data is stored. The feedback response data is read from the area
24
a
that has been selected according to the address signal, and is supplied to the DAC
25
. The DAC
25
converts the feedback response data to an analog signal and sends the analog signal to the adder
13
.
The time needed for the operation of the feedback filter
22
is the decoding time of the decoder
23
plus the reading time of the feedback response data. This time is shorter than the operation time of the feedback filter
16
in FIG.
1
. The use of the DFE
21
therefore has an improved reading speed.
The level of a read signal (Lorentz pulse) at a point of a magnetic variation, read by a hard disk device, may drop depending on the state of a recording medium or the read head. Further, a read signal having a level necessary for decision may not be obtained due to noise. In such a case, the decision unit
14
makes a decision error, causing erroneous data to be stored in the shift register
15
. The erroneous data is supplied to the adder
13
, resulting in divergence of the feedback loop. At this time, the DFE
21
continuously outputs reproduced signals of one state (“0” or “1”). That is, the feedback loop is temporarily stabilized to a fixed state, and will only return to the normal state after a considerable time. While the DFE
21
is outputting an erroneous reproduced signal, the hard disk device repeats the read operation on the same area of the magnetic disk. This elongates the data reading time.
When the frequency of the read signal changes according to the position of the read data on the magnetic disk, it is necessary to quickly change the feedback response data stored in the RAM
24
in accordance with the frequency. Rewriting all the feedback response data however takes time. The rewriting time interferes with speeding up the read operation.
More specifically, a hard disk device manages data in accordance with tracks formed concentrically on a magnetic disk and sectors which are radial segments of the recording surface. The same amount of data is recorded on the individual sectors. The closer to the center of the magnetic disk a sector is located, therefore, the higher the recording density becomes. When such a magnetic disk is rotated at a constant velocity, the symbol rate (the number of bits per unit time) of a signal read from the magnetic disk increases as the reading sector gets closer to the center of the magnetic disk. The frequency of the read signal therefore changes in accordance with the position of the reading sector.
FIG. 3
is a schematic block diagram of a conventional signal processor
213
. A head unit
212
, such as an MR (Magneto Resistive) head reads data recorded on a magnetic disk
211
, and sends a read signal RD having a voltage waveform (reproduced waveform from the magnetic disk) according to the status (1 or 0) of the read data to the signal processor
213
. A variable gain amplifier (VGA)
214
amplifies the read signal RD and sends the resultant signal having a predetermined amplitude to a decision feedback equalizer (DFE)
215
.
As shown in
FIG. 4
, the DFE
215
includes a prefilter
216
, an adder
217
, a decision unit
218
, a shift register
219
and a feedback filter
220
. An A/D converter (ADC)
222
in a timing clock reproduction PLL circuit
221
receives the output signal
Horibe Koji
Moriuchi Tsunehiko
Nakano Manabu
Nakata Yoshitaka
Sawada Masaru
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Phu Phuong
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