Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-08-02
2004-09-14
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S550000, C708S603000
Reexamination Certificate
active
06792442
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a signal processor and a multiply-accumulate unit with a rounding function for use in such a signal processor.
BACKGROUND ART
Signal processors read data from memory and process the read data in various ways, i.e., processes of addition, subtraction, logical operation, and multiplication. The processing capability of signal processors are highly increased by incorporating a multiply-accumulate unit which can execute, in one processor cycle, multiply-accumulate operations that frequently appear in signal processing program such as image processing, sound processing, or the like.
FIG. 1
of the accompanying drawings shows a conventional signal processor having several execution units, registers, and memory. The signal processor shown in
FIG. 1
is introduced in “IEEE VLSI SIGNAL PROCESSING, VI”, pp. 93-101, 1993.
As shown in
FIG. 1
, the conventional signal processor has eight 40-bit registers hereinafter referred to as “registers
50
”), MAC (multiply-accumulate) unit
52
, MUX (multiplexer)
53
, ALU (arithmetic and logical unit)
54
, BSFT (barrel shift unit)
55
, X memory
57
x
, and Y memory
57
y
. X memory
57
x
and Y memory
57
y
are hereinafter referred to as memory
57
x
and memory
57
y
, respectively.
Memory
57
x
and memory
57
y
are connected to registers
50
by respective data buses
58
x
,
58
y
. MAC unit
52
, ALU
54
, MUX
53
, and BSFT
55
are connected to output lines
51
a
,
51
b
, and
51
c
from registers
50
.
MAC unit
52
carries out multiply-accumulate operations. ALU
54
carries out an arithmetic or logical operation using an immediate value imm. selected by MUX
53
or a value from registers
50
. BSFT
55
carries out an arithmetic or logical shift using an immediate value imm. selected by MUX
53
or a value from registers
50
.
Multiply-accumulate operations that frequently appear in signal processing program are operations to perform a multiplication and an accumulation according to the following equation (1):
A=A+B×C
(1)
Specifically, the product of multiplicand B and multiplier C is added to addend A on the right side of the equation (1), and the sum is placed on the left side A of the equation (1). In most cases, addend A on the right side of the equation (1) is the result of multiply-accumulate operations that are frequently performed, while it may be read from memory in some cases. Operations that are represented by the equation (1) where the symbol “+” on the right side of the equation (1) is replaced with the symbol “−” are also referred to as multiply-accumulate operations.
In general multiply-accumulate units which deal with fixed-point numerical data, multiplicand B and multiplier C on the right side of the equation (1) are usually expressed in 16-bit wide because of practical and economical reasons. Since the product of multiplicand B and multiplier C becomes 32-bit wide at maximum, each of addend A on the right side of the equation (1) and the sum A on the left side of the equation (1) need to be expressed in 32-bit wide or more.
For the above reason, general signal processors have 32-bit registers or more to save the results of multiply-accumulate operations. When two 16-bit data are held in one register of such a signal processor, they are placed in 15th-0th bits or 31st-16th bits of the register.
Let us describe the multiply-accumulate operation according to the equation (1) which is carried out by the conventional signal processor shown in
FIG. 1
with reference to
FIG. 2
of the accompanying drawings.
FIG. 2
shows a sequence to perform a multiply-accumulate operation with registers
50
and MAC unit
52
of the conventional signal processor shown in FIG.
1
.
Multiplicand B, multiplier C, and addend A on the right side of the equation (1) are read from memory connected to the signal processor into register
502
, register
503
, and register
501
, respectively.
Multiplicand B and multiplier C may be placed in either 31st-16th bits or 15th-0th bits of registers
502
,
503
. It is assumed here that multiplicand B is placed in 31st-16th bits of register
502
and multiplier C is placed in 15th-0th bits of register
503
. Addend A is placed in all the bits of register
501
. In
FIG. 2
, numerals shown beneath registers
501
,
502
,
503
indicate bit positions therein.
Then, addend A is stored in ACC (accumulator)
523
of MAC unit
52
. Multiplicand B and multiplier C are supplied to multiply unit
521
in MAC unit
52
, which calculates the product of multiplicand B and multiplier C. The calculated product of multiplicand B and multiplier C is added to addend A from ACC
523
by adder/subtractor (±)
522
. The sum produced by adder/subtractor
522
is temporarily stored in ACC
523
, and written back via output line
56
into register
501
which has stored addend A.
Now, let us consider a process of reading an addend as 16-bit data from memory, performing a certain multiply-accumulate operation on the added, and saving the result as 16-bit data in memory on the conventional signal processor shown in FIG.
1
. In the process, all input and output data are 16-bit wide regardless of interim data sizes.
The above process occurs when the multiplicand or multiplier in a multiply-accumulate operation is used as the addend in another multiply-accumulate operation. In this process, since all the addend, the multiplicand, and the multiplier are 16-bit wide, the result may possibly cause an overflow depending on the values of the addend, the multiplicand, and the multiplier. However, the multiply-accumulate operation can be performed without an overflow if the addend, the multiplicand, and the multiplier are arranged in a suitable range.
Let us describe the multiply-accumulate operation in the above process on the conventional signal processor shown in
FIG. 1
with reference to
FIG. 3
of the accompanying drawings. In
FIG. 3
, multiplicand B, multiplier C, and addend A are read from memory connected to the signal processor into 31st-16th bits of register
502
, 15th-0th bits of register
503
, and 31st-16th bits of register
501
, respectively.
When addend A expressed as fixed-point 16-bit data is read into register
501
, the sign of addend A is inserted into 39th-32nd bits, addend A into 31st-16th bits, and “0” into 15th-0th bits. A state in which the data are stored in registers
501
,
502
,
503
is referred to as state
50
n
. A state of the registers after the multiply-accumulate operation is referred to as state
50
n
1
. A state of the registers after the result is rounded off is referred to as state
50
n
2
.
In state
50
n
1
which follows state
50
n
, the result A+B×C is stored in register
501
. In state
50
n
2
, the result of the multiply-accumulate operation, which is 40-bit wide, is rounded off into 16 bits by ALU
54
, and the rounded result is stored in register
501
. Finally, the rounded result is stored in memory.
There are two problems in the above processing sequence. The first problem is that the data size of addend A read from memory and the data size of an addend required by MAC unit
52
are different from each other. Since addend A is 16-bit data, it has to be expanded into 40-bit data for multiply-accumulate operations. Therefore, two 16-bit addends cannot be placed in one register.
The second problem is that the data size of the result of the calculation performed by the MAC unit and the data size of the result when it is stored in memory are different from each other. Because the MAC unit of the conventional signal processor outputs a 40-bit result, when it is to be stored as 16-bit data into memory, the 40 bits need to be rounded off into 16 bits. Consequently, a rounding process has to be carried out in addition to the multiply-accumulate operation.
If the bus size between memory and the register is increased to 32 bits in order to improve performance of the conventional signal processor, then two 16-bit data can simultaneously be read through each data bus.
Let us analyze mu
Dickstein , Shapiro, Morin & Oshinsky, LLP
NEC Corporation
Ngo Chuong Dinh
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