Signal processing system employing two bit ternary signal

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C341S144000, C341S143000, C381S117000

Reexamination Certificate




1. Field of the Invention
The present invention relates to a digital signal processor. A preferred embodiment of the invention relates to a digital audio signal processor. For convenience, reference will be made herein to audio signal processing, but the invention is not limited to audio signals.
2. Description of the Prior Art
It is well known to convert analogue signals to digital signals using differential quantization. In differential quantization a signal is sampled, and the difference between the value of a sample and a prediction of the value of the sample is quantized. The prediction may be the previous sample.
In general principle the difference can be quantized and represented by an m-bit signal where m is any integer, greater than or equal to one.
Common values of m in practice include 1, 8 and 16. Except for m=1, the differences are represented by signed numbers, e.g. 2's complement numbers. A 1-bit signal represents 2 signal levels. Greater numbers of bits represent greater numbers of levels. For example an 8 bit signal represents 256 levels.
A 1-bit digital audio signal processor has been proposed in for example GB-A-2 319 931. The processor includes Delta-Sigma Modulator (DSM) filter sections. A 1-bit digital signal processor produces a 1-bit output that contains an audio signal which is obscured by quantization noise to an unacceptable level. It is imperative that the noise spectrum is suitably shaped to place as much of the noise as possible outside the audio signal band. The noise is produced mainly by the quantization of the audio signal to 1-bit.
A DSM filter section is designed to suitably shape the noise to minimise the noise in the audio band. A DSM filter section typically includes, amongst other circuits, at least one multiplier and a quantizer. The multiplier forms the product of an n-bit coefficient and the 1-bit signal. The quantizer re-quantizes the product as a 1-bit signal. The other circuits of a DSM filter section typically include delay elements and adders.
Whilst processing a 1-bit signal involves difficult quantization noise shaping it has advantages of simplicity of hardware. A 1-bit multiplier for example is a relatively simple circuit. Furthermore a 1-bit signal processor has the known advantages of an inherently serial structure, and a phase response and distortion approaching that of a high quality analogue system whilst retaining the advantages of digital techniques.
It is desired to reduce quantization noise and yet retain the many benefits of a 1-bit signal processing system.
According to one aspect of the present invention, there is provided a digital signal processing system in which differentially quantized data is represented by a 2-bit digital signal representing only 3 levels of which one level is zero and the other 2 levels are more positive and more negative respectively than zero.
The provision of such a differentially quantized digital signal, referred to hereinafter as a “ternary signal”, having 2 bits representing only 3 levels produces better signal to noise ratio than a 1-bit signal, making a DSM filter section easier to design for the purpose of noise shaping. Also with the 2 bit representation of the 3 levels, in a preferred embodiment, only a minimal modification needs to be made to the multiplier(s) and the quantizer of what is otherwise a DSM filter section of a 1-bit signal processor. The modification is very cost effective.
The three levels may be represented by 11 for a positive increment relative to zero, 00 for a negative increment relative to zero and 01 or 10 for zero. It will be noted that two signal lines of a 2-bit parallel bus carrying the two bits may be reversed without affecting the values represented by the ternary signal.
The ternary signal used in the present invention differs from a “conventional” 2 bit signal in that a conventional 2 bit signal represents four levels represented by 00, 01, 10, 11 respectively. The represented levels are either asymmetric with respect to zero or none of them represents zero per se. A signal processor using such a conventional 2 bit signal requires more gates than the ternary signal used in the present invention and is thus less cost effective than the present invention.
According to another aspect of the invention, there is provided a signal processing system comprising a plurality of Delta Sigma Modulators (DSMs) in cascade, at least one of the DSMs being arranged to receive an r bit signal and to output a q bit signal, where at least one of r and q is a ternary signal having two bits which represent only three values, of which one value is zero, and the other two values represent a positive value and a negative value respectively.
The ternary signal reduces high frequency noise, allowing the design of cascaded DSMs to be simpler because noise induced instability is reduced.

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