Signal processing device, signal processing method,...

Details Signal processing device, signal processing method,... Signal processing device, signal processing method,...

2005-07-12

2005-07-12

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Increasing converter resolution

C341S143000, C341S144000

Reexamination Certificate

active

06917317

ABSTRACT:
A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F−k (where k is an integer) or a F value itself to the ΔΣ modulator (33), and circuit means (34through38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator (33) receives a particular F value (e.g., F=2n−1).

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