Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2003-01-14
2004-06-08
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S143000
Reexamination Certificate
active
06747586
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing device and a D/A converter, and more particularly to a D/A conversion technique used in a signal processing device including an analog-digital mixed loop having a digital section and an analog section for converging a loop output to a target value through the analog-digital mixed loop.
FIG. 14
illustrates a configuration of a reproduction signal processing device as an example of a signal processing device having an analog-digital mixed loop. A pickup
1
reads out information recorded on a recording medium
3
such as an optical disk or a magnetic disk that is rotated by a spindle motor
2
, and outputs the information as a reproduction signal to a variable-gain amplifier
4
. The amplitude of the reproduction signal is adjusted by the variable-gain amplifier
4
to be in conformity with the input dynamic range of an A/D converter
6
. After the noise of the signal in high-frequency band is eliminated through an analog filter
5
, the signal is quantized by the A/D converter
6
into a digital signal DT
0
.
The digital signal DT
0
is input to a digital signal processing block
7
and a PLL block
8
, which extract recorded data DT
1
and a clock CK
1
, respectively, from the digital signal DT
0
. Moreover, the digital signal DT
0
is fed back to the analog section through an offset adjustment block
9
and a gain adjustment block
10
. The offset adjustment block
9
produces an analog control signal based on the digital signal DT
0
so as to correct the offset of the A/D converter
6
. The gain adjustment block
10
produces an analog control signal based on the digital signal DT
0
so as to correct the gain factor of the variable-gain amplifier
4
.
There is an analog-digital mixed loop also in the PLL block
8
.
FIG. 15
illustrates an internal configuration of the PLL block
8
. While the PLL block
8
is in the frequency detection mode, a frequency comparator
82
calculates the frequency error between a fed-back signal (a signal obtained by dividing the frequency of the output clock CK
1
by a frequency divider
89
) and the digital signal DT
0
. A loop filter
84
produces a digital control signal DT
11
based on the error amount. Then, the digital control signal DT
11
is converted into an analog control signal DT
12
by a D/A converter
86
. A VCO (Voltage Controlled Oscillator)
88
outputs a corrected clock CK
1
based on the analog control signal DT
12
.
A current-cell type D/A converter, which is capable of operating at a high speed and has a high resolution, is used as the D/A converter
86
in the PLL block
8
.
FIG. 16
illustrates an internal configuration of the current-cell type 8-bit D/A converter
86
. The received 8-bit digital control signal DT
11
is stored in a register section
861
in synchronization with the system clock. Then, the lower four bits are used for turning ON/OFF a group of weighted current sources
863
, while the upper four bits are decoded into 15-bit data by a decoder section
862
. The 15-bit data is used for turning ON/OFF a number of current cells (16I
0
) in a current cell matrix
864
based on the value of the upper four bits.
Assume a case where “00101100” is input, as the digital control signal DT
11
, to the D/A converter
86
. In this case, since the lower four bits are “1100”, the output of the group of weighted current sources
863
is 8I
0
+4I
0
=12I
0
. Moreover, since the upper four bits are “0010”, two current cells of the current cell matrix
864
are turned ON to give an output of 16I
o
*232=I
0
. The output from the group of weighted current sources
863
and that from the current cell matrix
864
are added together by an output section
865
, which outputs 12I
0
+32I
0
=44I
0
as the analog control signal DT
12
.
In the PLL block
8
, the output frequency range of the VCO
88
, which is to be controlled, is quite wide. Therefore, a D/A converter having a high resolution is used as each of D/A converters
85
and
86
. However, a D/A converter having a high resolution takes, as its input, the digital control signal DT
11
having a large bit width, whereby the bit width for the internal operation becomes large. Thus, such D/A converters, particularly those of a current-cell type, lead to an increase in the circuit area and make it difficult to reduce the cost.
Moreover, not only the PLL block
8
, but in general, a signal processing device having an analog-digital mixed loop requires a D/A converter or a similar element. If the signal processing device requires a D/A converter or a similar element having a high resolution, there will be problems as those described above.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above, and has an object to provide a D/A converter in an analog-digital mixed loop with a reduced circuit area without sacrificing the resolution. It is also an object of the present invention to provide a signal processing device including such a D/A converter.
In order to achieve the objects set forth above, the present invention provides a signal processing device including a loop having a digital section for processing a digital signal and an analog section for processing an analog signal for converging a loop output to a target value through the loop, the signal processing device including a D/A converter for converting an m-bit (m is a positive integer) digital control signal received from the digital section into an analog control signal having substantially the same precision as that of the m-bit digital control signal so as to output the analog control signal to the analog section. The D/A converter includes: a bit modulation section for modulating the m-bit digital control signal into an n-bit (n is a positive integer: n<m) intermediate digital signal whose temporal average precision is substantially the same as the precision of the m-bit digital control signal; a D/A conversion section for converting the n-bit intermediate digital signal into an intermediate analog signal having a range corresponding to m bits; and an analog filter for smoothing the intermediate analog signal so as to output the smoothed signal as the analog control signal.
According to the present invention, the m-bit digital control signal is modulated by the bit modulation section into the intermediate digital signal while reducing the bit width from m bits to n bits. The temporal average precision of the intermediate digital signal is substantially the same as the precision of the m-bit digital control signal. Then, the intermediate digital signal is converted by the D/A conversion section into the intermediate analog signal having a range corresponding to m bits. As the intermediate digital signal, the intermediate analog signal also has a substantially m-bit precision. Finally, the intermediate analog signal is smoothed through the analog filter so as to be output as the analog control signal having substantially the same precision as the m-bit digital control signal. Therefore, according to the present invention, it is possible to reduce the bit width used for the operation inside the D/A converter, thereby reducing the circuit area of the signal processing device as a whole without sacrificing the resolution of the D/A converter.
It is preferred that the bit modulation section produces, from lower (m−n) bit/bits of the m-bit digital control signal, a 1-bit modulation bit whose temporal average precision is substantially the same as an (m−n)-bit precision so as to produce the n-bit intermediate digital signal by adding together upper n bit/bits of the m-bit digital control signal and the modulation bit.
In order to achieve the objects set forth above, the present invention also provides a signal processing device including a loop having a digital section for processing a digital signal and an analog section for processing an analog signal for converging a loop output to a target value through the loop, the signal processing device including a D/A converter for
Jeanglaude Jean Bruner
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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