Signal processing circuit to implement a Viterbi algorithm

Details Signal processing circuit to implement a Viterbi algorithm Signal processing circuit to implement a Viterbi algorithm

1995-08-30

1999-03-09

Le, Amanda

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

375341, 371 437, 371 438, 341 94, 341107, H03M 1312

Patent

active

058811060

ABSTRACT:
To carry out the processing operations relating to the implementation of a Viterbi algorithm, an integrated circuit comprising a processor and a coprocessor is made. The coprocessor is constructed so as to carry out operations of accumulation, comparison and selection in order to limit or reduce the work of a processor that would have to carry out these operations. By judiciously choosing the structure of the coprocessor, it is possible to make this co-processor sufficiently programmable so that it is suited to various situations of implementation of the Viterbi algorithm.

REFERENCES:
patent: 5181209 (1993-01-01), Hagenauer et al.
patent: 5220570 (1993-06-01), Lou et al.
patent: 5412669 (1995-05-01), Foland, Jr.
patent: 5432804 (1995-07-01), Diamondstein et al.
French Search Report from French Patent Application 94 10620, filed Sep. 5, 1994.
Globecom '90: IEEE Global Telecommunications Conference and Exhibition, `Communications: Connecting the Future` (CAT. No. 90CH2827-4), San Diego, CA, USA, Dec. 2-5, 1990, New York, USA. IEEE USA, pp. 1333-1337 vol. 2, Lou H., et al., "A Programmable Parallel Processor Architecture For Viterbi Detection".
Patent Abstracts of Japan, vo. 018, No. 608 (e-1633), Nov. 18, 1994 & JP-A-06 232923 (Sony Corp).

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