Dynamic information storage or retrieval – Control of storage or retrieval operation by a control... – Control of information signal processing channel
Reexamination Certificate
1997-01-14
2003-07-01
Neyzari, Ali (Department: 2653)
Dynamic information storage or retrieval
Control of storage or retrieval operation by a control...
Control of information signal processing channel
C369S047300, C369S059140, C369S059200
Reexamination Certificate
active
06587411
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an improvement of a read apparatus particularly in a CD-ROM drive system or a DVD (digital versatile disc) drive system.
FIG. 1
is a diagram showing the arrangement of a conventional read apparatus in a CD-ROM drive system.
A pickup head
12
irradiates a laser beam on the surface of a disk
11
, detects light reflected by the disk
11
, and converts the reflected light into an electrical signal. The output signal from the pickup head
12
is amplified to an RF signal by an amplifier
13
. This RF signal is input to a data slice circuit
14
.
The data slice circuit
14
has a function of binarizing the RF signal. Data which is binarized by the data slice circuit
14
is called an EFM (Eight to Fourteen Modulation) signal.
The EFM signal is input to a PLL (Phase-Locked Loop) and synchronizing signal separation circuit
15
. The PLL and synchronizing signal separation circuit
15
generates a synchronizing signal PFCK, a synchronizing clock CK, and a data signal DATA on the basis of the EFM signal. The data signal DATA and the synchronizing clock CK are input to an error correction circuit
16
. The error correction circuit
16
performs error correction processing using a correction RAM
17
.
When the data of a disk having a CD-ROM format is being read, the read apparatus is normally operated at a ×2 or more speed in many cases.
The corrected data is transferred to a CD-ROM decoder
18
. At this time, the clock for controlling the operation of the error correction circuit
16
is the synchronizing clock CK output from the PLL and synchronizing signal separation circuit
15
.
A clock selector
33
supplies the synchronizing clock CK output from the PLL and synchronizing signal separation circuit
15
or a clock output from a clock generator
25
to the error correction circuit
16
.
In read access to a CD-ROM, the data can be read at a high speed by operating the error correction circuit
16
with the synchronizing clock CK output from the PLL and synchronizing signal separation circuit
15
. This technique is described in detail in, e.g., Japanese Patent Application No. 6-339463 (filed on Dec. 29, 1994).
The CD-ROM decoder
18
corrects and buffers the data of the CD-ROM, and then transfers the data to a host computer
28
at a high speed.
When a disk which stores a digital audio signal is being read, the data is input to an audio D/A (Digital/Analog) converter
27
, and the audio data is output from the output terminal at a ×1 speed. Since the clock selector
33
supplies a crystal system clock generated by the clock generator
25
to the error correction circuit
16
, high-quality audio data can be obtained.
The synchronizing signal PFCK extracted from the EFM signal by the PLL and synchronizing signal separation circuit
15
is sent to a disk motor control circuit
22
and compared with the clock from the clock generator
25
. The disk motor control circuit
22
outputs, on the basis of the comparison result, a driving signal AFC (automatic speed control signal) for rotating the disk.
A driver
23
drives a disk motor
24
on the basis of the driving signal AFC such that the data read rate matches a predetermined rate.
A system controller
29
reads, via a microcomputer interface
26
, a correction flag or a compensation flag (error correction flag ECF) obtained by correction processing by the error correction circuit
16
.
The system controller
29
confirms the error generation frequency on the basis of the information of the correction flag or compensation flag. If it is determined that too many errors are generated by the high-speed read operation, the system controller
29
performs processing of reducing the data read rate.
A servo system signal read from the pickup
12
is sent to a pickup servo circuit
20
through an amplifier
19
and subjected to equalizing processing by the pickup servo circuit
20
. An output signal from the pickup servo circuit
20
is supplied to the actuator of the pickup
12
and a pickup feed motor
21
to control the operation of the actuator and the pickup feed motor.
The system controller
29
controls the CD-ROM decoder
18
and also controls the pickup servo circuit
20
via the microcomputer interface
26
.
To change the read rate, generally, the LSI often has an arrangement for realizing a ½
n
read rate with respect to the reference clock generated by the clock generator
25
. More specifically, if the maximum rate is ×4, a ×2 or ×1 read rate can be realized.
A CD system is originally an audio reproduction system. For this reason, a disk is normally rotated at a ×1 speed. However, when the CD system is applied to a CD-ROM drive, its data transfer rate is lower than that of the memory medium of a general computer.
It is an important challenge to raise the data transfer rate in consideration of read processing of recent large-capacity moving picture data. Recently, ×4 players have become popular, and the transfer rate is further increasing from ×4 to ×6, and to ×8.
In the prior art, however, when the read rate is to be changed, only a read rate corresponding to ½
n
(e.g., a ×4, ×2, or ×1 rate) the highest frequency can be realized as the disk rotation speed.
In addition, the CD disk standard is generally determined on the assumption of the ×1 speed. For this reason, for a disk having an extreme eccentricity or abnormal pit formation, the seek performance is degraded in high-speed rotation at, e.g., a ×4 or ×6 speed, resulting in erroneous data read.
As described above, for a disk having an eccentricity or abnormal pit formation, the conventional CD system cannot read the data by high-speed disk rotation. The data transfer rate must be extremely (discontinuously) reduced from, e.g., ×4 to ×2, and to ×1.
Accordingly, the seek time becomes long at a low speed, so the characteristics of the CD-ROM drive suitable for the high-speed read operation cannot be completely exhibited.
When the quartz oscillator is exchanged, or a VCO (Voltage Controlled Oscillator) is arranged, the disk can be rotated not only at a speed corresponding to ½
n
the highest frequency but also at an intermediate speed.
However, when a VCO is used to change the data read rate (data transfer rate), and the center frequency of the VCO is fixed, the data transfer rate can be changed only within the range of ±50% of the center frequency of the VCO.
Therefore, if the data transfer rate is changed in correspondence with the change in read rate, the higher and lower dynamic ranges with respect to the output frequency of the VCO become nonuniform. In the subsequent seek operation, the PLL loop cannot be stably locked in correspondence with the change in data transfer rate.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems, and has as its object to provide a signal processing circuit which can continuously change the read rate only by using one reference quartz oscillator, i.e., realize not only a read rate corresponding to ½
n
the highest frequency but also an intermediate read rate, and prevents the seek performance from being degraded even in a high-speed read operation, and a read apparatus using the circuit.
In order to achieve the above object, according to the present invention, there is provided a signal processing circuit comprising PLL/synchronizing signal separation means, having a voltage controlled oscillator capable of continuously changing a center frequency in accordance with a control voltage, for extracting a synchronizing clock and a synchronizing signal on the basis of data read from a disk, disk motor control means for rotating the disk and continuously changing a rotation speed of the disk in accordance with a control instruction, and conversion means for converting the control instruction into the control voltage, wherein the voltage controlled oscillator is controlled such that an output frequency b
Kabushiki Kaisha Toshiba
Neyzari Ali
LandOfFree
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