Dynamic magnetic information storage or retrieval – General recording or reproducing – Specifics of equalizing
Reexamination Certificate
2002-10-23
2003-12-09
Hudspeth, David (Department: 2651)
Dynamic magnetic information storage or retrieval
General recording or reproducing
Specifics of equalizing
Reexamination Certificate
active
06661594
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an information recording/reproducing apparatus, such as a magnetic disk apparatus and a magneto-optic disk apparatus, and a signal processing circuit used in those apparatuses, and more particularly to a circuit and a method for optimizing coefficients of an equalizer circuit having functions of estimating a detection or discrimination performance in optimization of the equalizer circuit, and optimization of various conditions in recording and reproduction, such as the write current value, DC offset compensation amount, etc, in apparatuses involving a partial response processing.
In an information recording/reproducing apparatus of this kind, it is necessary to optimally set various control parameters for recording and reproducing signals. To give an example, the optimization of the write current value in a magnetic disk apparatus is performed as follows. A write current value is set and recorded on a magnetic disk, then the bit error rate (BER) is measured while varying the phase of the discrimination window of the phase discriminator, which is a detection circuit of the reproduced signal processing circuit, to measure the phase width (phase margin) of the discrimination window which provides a tolerable level of BER (e.g., 1.0E−8 or less).
FIG. 2
shows a so-called bucket curve. This measurement is performed each time the write current value is changed, and the phase margins at various write current values are obtained. As shown in
FIG. 3
, the relation between write current values and the corresponding phase margins are checked and the write current value at which the phase margin is greatest is taken as the optimum value.
In evaluation of the BER in an apparatus of phase discrimination system of this kind, in order to obtain a bucket curve as shown in
FIG. 2
, a length of time at least in the order of minutes is required. It follows therefore that several minutes are required only to perform the optimization of the write current mentioned above.
In an actual optimization process, in addition to the write current value, other optimization parameters include the compensation amount (in what is referred to as write pre-compensation) of the flux reversal positions of the write current, equalizer circuit characteristics and detection levels of the error detector. More importantly, since those parameters are evaluated using a random pattern, they cannot be evaluated independently of each other. For this reason, in order to optimize the parameters with high accuracy, measurement of the bucket curve is preferably performed as many times as the product of the number of parameters and the number of partitions of the parameters, so that a vast length of time is required for the whole optimization process. If there are great variations among the magnetic heads and the recording/reproducing circuits, it is necessary to perform this optimization process for individual apparatuses and magnetic heads, so that a much greater length of time is required.
In evaluation of the BER by amplitude detection system, on the other hand, the technique disclosed in JP-A-3-144969 is well known. This method is such that a sequence of digital signals input to the detector of the apparatus are compared with a sequence of reference signals to measure a histogram of error values to thereby estimate a BER of the apparatus. The number of bits required to measure the histogram with high accuracy is on the order of thousands or tens of thousands at most, and this number is far smaller than one in the above-mentioned case (1.0E+8 bits or greater) using the phase detection system which measures the BER directly, and hence the time required to optimize the parameters is much shorter.
In the evaluation based on the estimation of the BER in the apparatus of amplitude discrimination system revealed in JP-A-3-144969, however, a relatively large scale evaluation device is required for measuring a histogram of error values. It is required to determine error values in real time and install counters or memories as many as the number of the histograms measured. If this measurement of the histograms is made inside the apparatus, an increase in the scale of the circuit is inevitable. If histograms are measured outside the apparatus while monitoring the input signal of the detector on the circuit board, measurement has to be performed at the bit rate of the apparatus, which poses a great difficulty in mounting or packaging the measuring apparatus in the case of an apparatus adapted to operate at high data transmission rate exceeding 100 Mbps.
With regard to the technique of optimizing the tap coefficients of an equalizer circuit, there is a method disclosed in JP-A-2-150114. In this publication, looking at the fact that the reproduced waveform (so-called solitary magnetization reproduced waveform) which corresponds to a single flux reversal or magnetization reversal in an information recording/reproducing apparatus such as a magnetic disk apparatus or a magneto-optic disk apparatus is a waveform that has the leading and trailing foot portions formed substantially so symmetrically as to be simulated by a Lorentzian waveform, there are proposed coefficient compensation means and a method of a transversal type equalizer circuit with symmetric coefficients at three taps, in other words, a so-called cosine equalizer circuit, wherein in a format on the magnetic disk, a training area of several bytes is provided before user data to perform coefficient compensation in real time.
In a case where only one tap coefficient is to be optimized as in a cosine equalizer circuit, it is preferable to use the method disclosed in JP-A-2-150114 mentioned above. However, if data is to be recorded with high density, the resolution of the reproduced waveform deteriorates, the foot portions of the waveform trail long, and the symmetry of the reproduced waveform is disturbed, and consequently a sufficient equalizing performance cannot be obtained with a cosine equalizer circuit which roughly adjusts the amplitude characteristics only.
As coefficient compensation algorithms capable of obtaining optimum values for a plurality of tap coefficients with relatively high accuracy, sequential compensation type algorithms such as CLMS (clipped least means square) are well known. However, in an apparatus which restores a clock signal for an equalizer circuit from a signal obtained at the subsequent stage of the equalizer circuit, contention occurs between the phase characteristic of the equalizer circuit and clock phase due to tap coefficients of the equalizer becoming asymmetric in the coefficient compensation process, and because of this, the characteristics of the equalizer circuit do not settle. Moreover, a problem arises that the coefficients in the converged state unavoidably oscillate due to the delays of the equalizer circuit and the coefficient compensation circuit portion and also due to the effects of the finite bit number of the digital circuit, and for this reason, a sufficient performance cannot be obtained.
To execute the above-mentioned coefficient compensation operation, the head disk controller needs to cause the read gate to open when the head is located over a data area, and for this purpose at least ID must be able to be read even under a condition that the equalizer circuit is not in the optimized state. Therefore, it is required that a data pattern (a sync byte in this case) to demarcate an area for use with AGC/PLL from a data area be formed in a specific pattern easy to identify.
Furthermore, if a signal processing circuit is designed as a LSI, the scale of the circuit becomes large-size, so it is important to take into consideration the chip area, power consumption, the number of pins. cost, etc. It is desired that all components be packaged in a one-chip LSI. However, if power consumption is large, for instance, the signal processing circuit needs to be formed in two or more subdivided chips and hence it is important at what portion the circuit is to be divided
Hirai Tomoaki
Hirano Akihiko
Hori Yosuke
Minoshima Satoshi
Mita Seiichi
Hitachi , Ltd.
Hudspeth David
Mattingly Stanger & Malur, P.C.
Wong K.
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