Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1997-04-24
1999-11-23
Mai, Tan V.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
708503, G06F 700, G06F 744
Patent
active
059917849
DESCRIPTION:
BRIEF SUMMARY
This invention relates to a circuit for applying a predetermined algorithm to an input signal.
Such a circuit may be, for example, a circuit for encoding or decoding speech samples using ADPCM (Adaptive Differential Pulse Code Modulation).
ADPCM (Adaptive Differential Pulse Code Modulation) is a digital signal processing algorithm designed to reduce the bandwidth of Pulse Code Modulated Speech samples. CCITT recommendation G.721 (Melbourne 1988) describes the algorithm in detail as it pertains to the conversion of 64 kb/s .mu.-law or A-law PCM encoded speech to and from a 32 kb/s compressed format. ANSI recommendation T1-303, and CCITT rec G.726 are similar documents with extensions to 40 k/s and 24 kb/s and 16 kb/s bit rates. The actual implementation of an ADPCM algorithm in a real time speech processing application may take various different forms ranging from a computer program, instruction code on a commercially available DSP chip, ASIC logic chip, or a custom integrated circuit.
This invention is concerned with implementation in the form of a custom chip. In the prior art, implementation has been achieved in this form by employing microprocessor technology using a high speed clock to run a circuit consisting of a multiplexed ALU (arithmetic logic unit) circuit, state machine, or micro-coded instruction based processor. The algorithm has to be coded as a stored program, and the power consumption involved is very substantial when fetching instructions, decoding and executing the instructions, which requires large data buses to be pulled up and down, continually charging and discharging CMOS transistor gates. Furthermore a lot of instructions are required to execute the program.
Analysis of prior art ADPCM devices available reveals that power consumption has not been optimized. In practice, the minimum power requirements are in the order of several hundred milliwatts.
Particularly in Pair Gain (twisted pair line quadrupling) applications and Cordless Digital telephones (e.g. Personal Handy Phone handsets and base-stations), power consumption is becoming a major preoccupation of circuit designers.
Pair Gain is a method of increasing the number of subscribers that may simultaneously use a single analog twisted pair telephone line for independent two-way conversations. A/D and D/A converters (CODEC'S) are used to digitize the speech channels into 64 kb/s A-law or .mu.-law PCM, after which one or more ADPCM devices are used to compress the 64 kb/s streams to 32 kb/s. These 32 kb/s channels are then merged into a single ISDN Ubus transceiver device to transmit the digitized signals as one 144 kb/s (2B+D) base-band modem signal onto a single twisted pair copper cable. At the distant end of the cable, similar devices are used to reconvert the signals back to analog form to interface with separate analog telephones.
Pair Gain equipment is used in locations where the cost of installation of copper pair cable for additional telephone lines proves to be prohibitively expensive (or more expensive than the Pair Gain equipment).
Because it is desirable that the Pair Gain equipment circuitry be line powered (i.e. powered by DC on the line itself), it is necessary that the power consumption of the devices used be minimized. There is a relationship between maximum line length possible with the Pair Gain equipment and the power consumption of the circuit. This means that the current consumption of the ADPCM device directly affects performance parameters of the Pair Gain product.
Cordless digital telephones that conform to the CT2 (Cordless Telephone 2) specification or other specifications use a codec to convert signals from analog to digital and back, as well as ADPCM compression to 32 kb/s to reduce the bandwidth of the digital signal before transmission. Since the telephone set must be battery operated, the power consumption of the components will directly affect the number of hours of usage before the battery must be recharged. This means that the current consumption of the ADPCM device directly affects performance p
REFERENCES:
patent: 4799182 (1989-01-01), Marwood
patent: 4858163 (1989-08-01), Boreland
Shanbhag et al, "A high-speed Architecture for ADPCM Codec", 1992 IEEE Int. Symposium on Circuits and systems, vol. 3 of 6, pp. 1499-1502, May 10, 1992.
Aly, "24-Channel 32Kb/s ADPCM Transcoder Using the CCITT Recommendation g. 721", ICASSP 86 Proceedings vol. 1, pp. 349-352, Apr. 1986.
Mai Tan V.
Mitel Corporation
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