Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2005-01-21
2008-10-14
Malzahn, David H (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07437393
ABSTRACT:
Signal processing apparatus or non-integer divider with a small circuit scale and a fractional N-PLL synthesizer comprising same. An adder2and a delay device4constitute a 20-bit input accumulator and its input is connected to a signal input terminal1. Adder8and a delay device10constitute a 9-bit input accumulator. Into higher 8 bits of its input, higher 8 bits of the output of the accumulator comprising the adder2and the delay device4are inputted. The output of a 3-input NAND gate30is connected to the remaining lowest bit input. An adder13and a delay device15constitute a 6-bit input accumulator. Higher 6 bits of an output signal of the adder8are inputted into this 6-bit input accumulator. An adder18and a delay device20constitute a 4-bit input accumulator. Higher 4 bits of an output signal of the adder13are inputted into this 4-bit input accumulator. Lower 3 bits of output data of the 4-bit delay device20are inputted into the 3-input NAND gate30. Overflow signals22, 23, 24, and25of the respective accumulator are inputted into a signal processing part27, which sums the overflow signal22, the result of first order differentiation of the overflow signal23, the result of second order differentiation of the overflow signal24, and the result of third order differentiation of the overflow signal25, and then outputs the summing result from a terminal28.
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Malzahn David H
NEC CORPORATION
Sughrue & Mion, PLLC
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