Television – Bandwidth reduction system – Data rate reduction
Patent
1995-03-13
1998-01-06
Chin, Tommy P.
Television
Bandwidth reduction system
Data rate reduction
348405, 348421, 348422, H04N 718
Patent
active
057060568
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
The present invention relates to a signal processing apparatus, and more particularly to an improvement of recording or reproducing apparatus for a digital video tape recorder (D-VTR) for discrete cosine transforming (DCT) video signal in order to compress amount of information thereof and recording it.
2. Background Art
Heretofore, as this type of D-VTR, there is one shown in FIG. 1. In FIG. 1, 1 generally denotes the D-VTR. A digital video signal S1 (FIG. 2(B)) input from a predetermined video signal generating unit is input to a DCT shuffling circuit 2. The DCT shuffling circuit 2 has a DCT address circuit 3 in association therewith, a vertical synchronizing signal S.sub.V (FIG. 2(A)) is input to the DCT address circuit 3.
Accordingly, the DCT shuffling circuit 2 divides the digital video signal S1 into DCT blocks of 8 columns.times.4 rows for each one field by shuffle address generated by the DCT address circuit 3 on the basis of the vertical synchronizing signal S.sub.V. The DCT shuffling circuit 2 collects 10 blocks of the DCT blocks from their respective positions discretely located from each other within a screen to generate shuffle data S2 (FIG. 2(C)), and outputs the shuffle data S2 to the following DCT conversion circuit 4.
Here, the DCT shuffling circuit 2 performs shuffling processing by each one field. Thereby, the shuffle data S2 output from the DCT shuffling circuit 2 is supplied to the DCT conversion circuit 4 at a timing delayed by one field time period T2 from the digital video signal S1 as shown in FIG. 2(C).
The DCT conversion circuit 4 performs discrete cosine transform to data of each DCT block and supplies DCT data S3 to a quantization delay circuit 5 and a quantization level detecting circuit 6. The quantization level detecting circuit 6 detects a quantization level (quantization width) for achieving a target compression rate for the DCT data S3. Since, at this time, about ten-block time period is required as the signal processing time in the quantization level detecting circuit 6, the quantization delay circuit 5 delays the DCT data S3 by the signal processing time, and supplies it to a quantization circuit 7 as a quantization delay output data S5. Accordingly, the quantization delay output data S5 is input to the quantization circuit 7 at the same timing as quantization level data S4 which is output from the quantization level detecting circuit 6 at a time point t3 delayed by a 10-block time period T3 from the shuffle data S2 as shown in FIG. 2(D).
The quantization circuit 7 quantizes the quantization delay output data S5 supplied from the quantization delay circuit 5 based on the quantization level data S4 supplied from the quantization level detecting circuit 6 in order to compress amount of information thereof. At this time, the quantization circuit 7 detects a maximum value, a minimum value, and a mean value etc., of quantization level within one field, on the basis of a period signal for each one field obtained from the vertical synchronizing signal S.sub.V at a vertical counter 8 provided in association therewith, and outputs the result as detection data S6 to a quantization monitor (not shown) to monitor the state of compression of data at the quantization circuit 7.
Further, quantization data S7 obtained from the quantization circuit 7 is supplied to a variable-length coding circuit 9. The variable-length coding circuit 9 performs variable-length coding to the quantization data S7 to generate variable-length coding data S9 having a block length prescribed in a format, and outputs it to an error correcting outer coding circuit 11.
The error correcting outer coding circuit 11 generates an error correcting outer code for correcting an error occurred in the manner of a burst, on the basis of a timing obtained from the vertical synchronizing signal S.sub.V at a parity timing circuit 12 which is provided in association therewith, and the result is added to the variable-length coding data S9 and is output to a track shuffling circuit 13.
The track
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Chin Tommy P.
Frommer William S.
Rao Anand S.
Sinderbrand Alvin
Sony Corporation
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