Television – Synchronization – Sync generation
Reexamination Certificate
1999-05-18
2002-08-13
Harvey, David E. (Department: 2614)
Television
Synchronization
Sync generation
C348S521000, C348S637000
Reexamination Certificate
active
06433829
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal processing apparatus that allows the “beginning” position and the “end” position of a vertical blanking signal of a television signal to be set.
2. Description of the Related Art
In a deflecting system of a television (TV) set, a circuit block that generates a horizontal drive (H_DRV) signal and a vertical drive (V_DRV) signal also generates a vertical blanking signal. Conventional TV sets have their designated signal formats such as a NTSC format and a PAL format. Thus, in the conventional TV sets, it is necessary to select only a picture blanking timing.
However, in recent years, a point-scan TV set and a multi-scan TV set have been developed. The point-scan TV set can display pictures that correspond to several signal formats. The multi-scan TV set can display pictures of any signal standard in its deflecting range. In these TV sets, the timing of the vertical blanking signal should be freely set.
Timings necessary for generating the vertical blanking signal are the “beginning” and “end” positions thereof. The “beginning” position of the vertical blanking signal is necessary for hiding the lower portion of a picture on the TV screen. On the other hand, the “end” position of the vertical blanking signal is necessary for hiding the upper portion of a picture on the TV screen.
Technically, it is easy to generate a timing of the “end” position of the vertical blanking signal. As shown in
FIG. 1
, a counter that starts counting with a vertical synchronous signal (Vsync) and counts up the number of horizontal synchronous signals (Hsync) is used. When the count value of the counter becomes a predetermined value, a timing pulse that represents the “end” position of the vertical signal is output.
On the other hand, it is difficult to generate a timing for the “beginning” position of the vertical blanking signal. As shown in
FIG. 2
, when the number of picture signal formats is one, since the last value of the above-described counter (namely, the immediately preceding value of the vertical synchronous signal) is known, the “beginning” position can be obtained by the reverse-calculation of the last value of the counter. However, when there are various picture signal formats, the last value of the counter is unknown. Thus, the “beginning” position cannot be obtained by the reverse-calculation. Consequently, the “beginning” position of a vertical synchronous signal is inevitably treated as the “beginning” position of a vertical blanking signal. It is difficult to generate a timing of the “beginning” position of a vertical blanking signal earlier than a vertical synchronous signal. Thus, the “beginning” position of the vertical blanking signal cannot be freely set.
However, in recent TV sets, as shown in
FIG. 3A
, a 16:9 picture signal is displayed on a TV set with an aspect ration of 4:3. In contrast, as shown in
FIG. 3B
, two pictures of 4:3 picture signals are horizontally displayed in a row on one wide TV set with an aspect ratio of 16:9. In other words, raster scan pictures are displayed as under scan pictures. When only over-scan pictures are displayed, inaccurate timings of the “beginning” and “end” positions of the vertical blanking signal are permitted to some extent. However, in the case of under-scan pictures, a vertical blanking signal cannot be hidden. Thus, the timings of the “beginning” and “end” positions of the vertical blanking signal are very important. In addition, the timings of the “beginning” position and the “end” position of a vertical blanking signal should be flexibly selected.
Moreover, conventional TV sets cannot deal with irregular modes of which an interlace signal is forcedly locked to the state of a non-interlace signal or vice versa.
OBJECTS AND SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a signal processing apparatus that allows the “beginning” position and “end” position of a vertical blanking signal to be set irrespective of an input signal and of the number of lines between vertical synchronous signals.
Another object of the present invention is to provide a signal processing apparatus that can deal with a forcedly locked interlace signal or a forcedly locked non-interlace signal.
A first aspect of the present invention is a signal processing apparatus for setting a vertical blanking signal of an input television signal, comprising a first counter, synchronized with a horizontal synchronous signal, for counting up a count value thereof starting from a first value corresponding to a predetermined clock signal whose frequency is higher than the frequency of the horizontal synchronous signal, and a second counter for counting down a count value thereof starting from a second value, wherein immediately before the count value of the first counter is reset at a particular timing corresponding to the vertical synchronous signal and the horizontal synchronous signal, the second counter loads the count value of the first counter as the second value, and wherein immediately before the second value is loaded to the second counter, the count value of the second counter becomes the first value.
A second aspect of the present invention is a signal processing apparatus for setting a vertical blanking signal of an input television signal, comprising a clock signal generating means, synchronized with a horizontal synchronous signal, for generating a second clock signal corresponding to a first clock signal and a field signal, the first clock signal operating at a frequency higher than the frequency of the horizontal synchronous signal, a first counter for counting up a count value thereof starting from a first value corresponding to the second clock signal, and a second counter for counting down a count value thereof starting from a second value corresponding to the first clock signal, wherein immediately before the count value of the first counter is reset at a particular timing corresponding to a vertical synchronous signal and the second clock signal, the second counter loads the count value of the first counter as the second value.
The count value immediately before the resetting of the up counter is loaded to the down counter. The down counter counts down the count value starting from the loaded count value. When the value of the down counter becomes a predetermined value, it is determined that the vertical blanking signal “begins”. Thereafter, when the up counter becomes a predetermined value, it is determined that the vertical blanking signal “ends”. With a field signal, a timing of a deviation of a ½ horizontal interval is fixed to a horizontal synchronous signal. Thus, a forced non-interlace mode and a forced interlace mode can be dealt.
The above, and other, objects, features and advantage of the present invention will become readily apparent from the following detailed description thereof which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 4679080 (1987-07-01), Bashford
patent: 4803552 (1989-02-01), Marin
patent: 4-3662 (1992-01-01), None
patent: 4-192971 (1992-07-01), None
patent: 63-219273 (1998-09-01), None
patent: 93/01681 (1993-01-01), None
Nagamine Takatomo
Takahashi Shinji
Harvey David E.
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
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