Signal processing apparatus for recovering a clock signal and a

Details Signal processing apparatus for recovering a clock signal and a Signal processing apparatus for recovering a clock signal and a

1989-08-10

1991-09-03

Olms, Douglas W.

Pulse or digital communications

Repeaters

Testing

375 87, 375 88, 375110, 328 56, H04L 2714

Patent

active

050460730

ABSTRACT:
A signal processing apparatus is provided for recovering the clock signal and data signal from an encoded information signal. The encoded signal which is to be processed includes first symbols exhibiting a first frequency representing logical ones and second symbols exhibiting a second frequency representing logical zeros. A tapped delay line produces a first recovered clock signal exhibiting a frequency approximately twice that of the clock rate of the data signal. Circuitry is provided for recovering the data signal and a second recovered clock signal which exhibits a frequency approximately equal to the clock rate of the data signal.

REFERENCES:
patent: 4322851 (1982-03-01), Vance
patent: 4462107 (1984-07-01), Vance
patent: 4752742 (1988-06-01), Akaiwa
"Single-Channel Phase-Coherent-FSK Bus Physical Layer"; May, 1988; Token-Passing Bus--IEEE 802.4 Draft K; pp. 173-186.

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