Signal processing apparatus for performing high speed arithmetic

Details Signal processing apparatus for performing high speed arithmetic Signal processing apparatus for performing high speed arithmetic

1993-03-23

1995-01-10

Ray, Gopal C.

Boots, shoes, and leggings

395800, 3642224, 3642378, 3642731, 364228, 3642719, 364DIG1, 364260, G06F 305, G06F 1520, G06F 132, G06F 900

Patent

active

053815530

ABSTRACT:
A signal processing apparatus enjoying a remarkably enhanced operation speed while ensuring accurate control capability due to data holding and learning control includes an A/D converter for converting an analog signal into a digital signal, a packet interface for generating a packet on the basis of the digital signal, a timing port controller for controlling the timing of operation of the A/D converter and generating output data on the basis of the packet, a power supply interruption detecting circuit for detecting a decrease in source voltage to thereby generate a power supply interruption detecting signal, and a data flow processor including a data store and a data flow loop for processing the packet in accordance with tag information contained in the packet. The data flow processor responds to the power supply interruption detecting signal to save electric power from consumption and hold the content of the data store.

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