Signal processing apparatus for correcting decoding errors

Details Signal processing apparatus for correcting decoding errors Signal processing apparatus for correcting decoding errors

1986-03-20

1988-05-24

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

047471034

ABSTRACT:
There is a signal processing apparatus for use in the error correction field for correcting errors in systems such as Reed Solomon code. This apparatus has three kinds of cells which execute the proceses in the decoding of the BCH code: namely, a syndrome cell to produce syndromes; a GCD (greatest common divisor) cell to produce an error position polynomial and an error evaluation polynomial; and an evaluation cell to estimate and correct errors in position and size. The required cells are one-dimensionally arranged in accordance with the error correcting capability of the code which is used. The algorithm for the signal processes in the conventional communication line is modified to the algorithm suitable for parallel processing. The signal processes can be executed using parallel processors due to the pipeline processes. Those dedicated cells can be realized by the hardwares, respectively. Each cell is controlled by only reference clock and synchronizing signal and the input and output data are time-sequentially multiplexed in the cell or process. Thus, this apparatus is fitted for multi-error correction and can be formed as an LSI because the circuit scale is small.

REFERENCES:
patent: 4162480 (1979-07-01), Berlekamp
patent: 4413339 (1983-11-01), Riggle et al.
patent: 4498175 (1985-02-01), Nagumo et al.
patent: 4527269 (1985-07-01), Wood et al.
patent: 4583225 (1986-04-01), Yamada et al.
patent: 4584686 (1986-04-01), Fritze

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